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[PowerPC] Support of ppc_fp128 in lowering of llvm.is_fpclass
PowerPC supports `ppc_fp128`, which is not an IEEE floating point type. The generic lowering of llvm.is_fpclass could not handle it properly. This change extends the generic lowering code to support `ppc_fp128`. The change was tested on emulator using runtime tests from https://reviews.llvm.org/D112933 and the patch for clang https://reviews.llvm.org/D112932. Differential Revision: https://reviews.llvm.org/D113908
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‎llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

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@@ -7439,6 +7439,14 @@ SDValue TargetLowering::expandIS_FPCLASS(EVT ResultVT, SDValue Op,
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if (Test == 0 || (Test & fcAllFlags) == fcAllFlags)
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return DAG.getBoolConstant(true, DL, ResultVT, OperandVT);
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// PPC double double is a pair of doubles, of which the higher part determines
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// the value class.
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if (OperandVT == MVT::ppcf128) {
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Op = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::f64, Op,
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DAG.getConstant(1, DL, MVT::i32));
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OperandVT = MVT::f64;
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}
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// Some checks may be represented as inversion of simpler check, for example
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// "inf|normal|subnormal|zero" => !"nan".
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bool IsInverted = false;

‎llvm/test/CodeGen/PowerPC/is_fpclass.ll

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@@ -0,0 +1,314 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr9 -verify-machineinstrs -o - %s | FileCheck %s
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define i1 @isnan_float(float %x) nounwind {
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; CHECK-LABEL: isnan_float:
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; CHECK: # %bb.0:
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; CHECK-NEXT: fcmpu 0, 1, 1
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; CHECK-NEXT: li 3, 0
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; CHECK-NEXT: li 4, 1
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; CHECK-NEXT: isel 3, 4, 3, 3
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; CHECK-NEXT: blr
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%1 = call i1 @llvm.is.fpclass.f32(float %x, i32 3) ; nan
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ret i1 %1
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}
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define i1 @isnan_double(double %x) nounwind {
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; CHECK-LABEL: isnan_double:
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; CHECK: # %bb.0:
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; CHECK-NEXT: fcmpu 0, 1, 1
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; CHECK-NEXT: li 3, 0
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; CHECK-NEXT: li 4, 1
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; CHECK-NEXT: isel 3, 4, 3, 3
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; CHECK-NEXT: blr
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%1 = call i1 @llvm.is.fpclass.f64(double %x, i32 3) ; nan
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ret i1 %1
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}
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define i1 @isnan_ppc_fp128(ppc_fp128 %x) nounwind {
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; CHECK-LABEL: isnan_ppc_fp128:
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; CHECK: # %bb.0:
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; CHECK-NEXT: fcmpu 0, 1, 1
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; CHECK-NEXT: li 3, 0
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; CHECK-NEXT: li 4, 1
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; CHECK-NEXT: isel 3, 4, 3, 3
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; CHECK-NEXT: blr
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%1 = call i1 @llvm.is.fpclass.ppcf128(ppc_fp128 %x, i32 3) ; nan
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ret i1 %1
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}
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define i1 @isnan_f128(fp128 %x) nounwind {
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; CHECK-LABEL: isnan_f128:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xscmpuqp 0, 2, 2
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; CHECK-NEXT: li 3, 0
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; CHECK-NEXT: li 4, 1
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; CHECK-NEXT: isel 3, 4, 3, 3
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; CHECK-NEXT: blr
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%1 = call i1 @llvm.is.fpclass.f128(fp128 %x, i32 3) ; nan
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ret i1 %1
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}
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define i1 @isnan_float_strictfp(float %x) strictfp nounwind {
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; CHECK-LABEL: isnan_float_strictfp:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xscvdpspn 0, 1
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; CHECK-NEXT: lis 4, 32640
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; CHECK-NEXT: mffprwz 3, 0
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; CHECK-NEXT: clrlwi 3, 3, 1
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; CHECK-NEXT: cmpw 3, 4
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; CHECK-NEXT: li 3, 0
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; CHECK-NEXT: li 4, 1
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; CHECK-NEXT: iselgt 3, 4, 3
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; CHECK-NEXT: blr
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%1 = call i1 @llvm.is.fpclass.f32(float %x, i32 3) ; nan
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ret i1 %1
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}
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define i1 @isnan_double_strictfp(double %x) strictfp nounwind {
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; CHECK-LABEL: isnan_double_strictfp:
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; CHECK: # %bb.0:
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; CHECK-NEXT: mffprd 3, 1
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; CHECK-NEXT: li 4, 2047
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; CHECK-NEXT: clrldi 3, 3, 1
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; CHECK-NEXT: rldic 4, 4, 52, 1
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; CHECK-NEXT: cmpd 3, 4
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; CHECK-NEXT: li 3, 0
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; CHECK-NEXT: li 4, 1
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; CHECK-NEXT: iselgt 3, 4, 3
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; CHECK-NEXT: blr
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%1 = call i1 @llvm.is.fpclass.f64(double %x, i32 3) ; nan
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ret i1 %1
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}
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define i1 @isnan_ppc_fp128_strictfp(ppc_fp128 %x) strictfp nounwind {
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; CHECK-LABEL: isnan_ppc_fp128_strictfp:
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; CHECK: # %bb.0:
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; CHECK-NEXT: mffprd 3, 1
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; CHECK-NEXT: li 4, 2047
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; CHECK-NEXT: clrldi 3, 3, 1
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; CHECK-NEXT: rldic 4, 4, 52, 1
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; CHECK-NEXT: cmpd 3, 4
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; CHECK-NEXT: li 3, 0
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; CHECK-NEXT: li 4, 1
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; CHECK-NEXT: iselgt 3, 4, 3
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; CHECK-NEXT: blr
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%1 = call i1 @llvm.is.fpclass.ppcf128(ppc_fp128 %x, i32 3) ; nan
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ret i1 %1
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}
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define i1 @isnan_f128_strictfp(fp128 %x) strictfp nounwind {
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; CHECK-LABEL: isnan_f128_strictfp:
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; CHECK: # %bb.0:
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; CHECK-NEXT: stxv 34, -16(1)
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; CHECK-NEXT: li 5, 32767
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; CHECK-NEXT: ld 4, -8(1)
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; CHECK-NEXT: ld 3, -16(1)
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; CHECK-NEXT: rldic 5, 5, 48, 1
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; CHECK-NEXT: clrldi 4, 4, 1
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; CHECK-NEXT: cmpld 4, 5
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; CHECK-NEXT: cmpd 1, 4, 5
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; CHECK-NEXT: crandc 20, 5, 2
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; CHECK-NEXT: cmpdi 1, 3, 0
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; CHECK-NEXT: li 3, 1
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; CHECK-NEXT: crandc 21, 2, 6
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; CHECK-NEXT: crnor 20, 21, 20
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; CHECK-NEXT: isel 3, 0, 3, 20
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; CHECK-NEXT: blr
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%1 = call i1 @llvm.is.fpclass.f128(fp128 %x, i32 3) ; nan
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ret i1 %1
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}
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define i1 @isinf_float(float %x) nounwind {
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; CHECK-LABEL: isinf_float:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xscvdpspn 0, 1
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; CHECK-NEXT: li 4, 1
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; CHECK-NEXT: mffprwz 3, 0
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; CHECK-NEXT: clrlwi 3, 3, 1
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; CHECK-NEXT: xoris 3, 3, 32640
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; CHECK-NEXT: cmplwi 3, 0
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; CHECK-NEXT: li 3, 0
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; CHECK-NEXT: iseleq 3, 4, 3
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; CHECK-NEXT: blr
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%1 = call i1 @llvm.is.fpclass.f32(float %x, i32 516) ; 0x204 = "inf"
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ret i1 %1
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}
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define i1 @isinf_ppc_fp128(ppc_fp128 %x) nounwind {
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; CHECK-LABEL: isinf_ppc_fp128:
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; CHECK: # %bb.0:
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; CHECK-NEXT: mffprd 3, 1
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; CHECK-NEXT: li 4, 2047
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; CHECK-NEXT: clrldi 3, 3, 1
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; CHECK-NEXT: rldic 4, 4, 52, 1
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; CHECK-NEXT: cmpd 3, 4
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; CHECK-NEXT: li 3, 0
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; CHECK-NEXT: li 4, 1
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; CHECK-NEXT: iseleq 3, 4, 3
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; CHECK-NEXT: blr
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%1 = call i1 @llvm.is.fpclass.ppcf128(ppc_fp128 %x, i32 516) ; 0x204 = "inf"
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ret i1 %1
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}
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define i1 @isinf_f128(fp128 %x) nounwind {
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; CHECK-LABEL: isinf_f128:
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; CHECK: # %bb.0:
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; CHECK-NEXT: stxv 34, -16(1)
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; CHECK-NEXT: li 5, 32767
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; CHECK-NEXT: ld 4, -8(1)
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; CHECK-NEXT: ld 3, -16(1)
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; CHECK-NEXT: rldic 5, 5, 48, 1
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; CHECK-NEXT: clrldi 4, 4, 1
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; CHECK-NEXT: xor 4, 4, 5
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; CHECK-NEXT: or 3, 3, 4
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; CHECK-NEXT: cntlzd 3, 3
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; CHECK-NEXT: rldicl 3, 3, 58, 63
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; CHECK-NEXT: blr
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%1 = call i1 @llvm.is.fpclass.f128(fp128 %x, i32 516) ; 0x204 = "inf"
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ret i1 %1
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}
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define i1 @isfinite_float(float %x) nounwind {
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; CHECK-LABEL: isfinite_float:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xscvdpspn 0, 1
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; CHECK-NEXT: lis 4, 32640
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; CHECK-NEXT: mffprwz 3, 0
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; CHECK-NEXT: clrlwi 3, 3, 1
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; CHECK-NEXT: cmpw 3, 4
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; CHECK-NEXT: li 3, 0
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; CHECK-NEXT: li 4, 1
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; CHECK-NEXT: isellt 3, 4, 3
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; CHECK-NEXT: blr
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%1 = call i1 @llvm.is.fpclass.f32(float %x, i32 504) ; 0x1f8 = "finite"
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ret i1 %1
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}
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define i1 @isfinite_f128(fp128 %x) nounwind {
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; CHECK-LABEL: isfinite_f128:
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; CHECK: # %bb.0:
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; CHECK-NEXT: stxv 34, -16(1)
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; CHECK-NEXT: li 4, 32767
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; CHECK-NEXT: ld 3, -8(1)
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; CHECK-NEXT: rldic 4, 4, 48, 1
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; CHECK-NEXT: clrldi 3, 3, 1
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; CHECK-NEXT: cmpd 3, 4
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; CHECK-NEXT: li 3, 0
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; CHECK-NEXT: li 4, 1
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; CHECK-NEXT: isellt 3, 4, 3
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; CHECK-NEXT: blr
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%1 = call i1 @llvm.is.fpclass.f128(fp128 %x, i32 504) ; 0x1f8 = "finite"
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ret i1 %1
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}
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define i1 @isnormal_float(float %x) nounwind {
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; CHECK-LABEL: isnormal_float:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xscvdpspn 0, 1
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; CHECK-NEXT: li 4, 1
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; CHECK-NEXT: mffprwz 3, 0
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; CHECK-NEXT: clrlwi 3, 3, 1
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; CHECK-NEXT: addis 3, 3, -128
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; CHECK-NEXT: srwi 3, 3, 24
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; CHECK-NEXT: cmplwi 3, 127
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; CHECK-NEXT: li 3, 0
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; CHECK-NEXT: isellt 3, 4, 3
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; CHECK-NEXT: blr
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%1 = call i1 @llvm.is.fpclass.f32(float %x, i32 264) ; 0x108 = "normal"
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ret i1 %1
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}
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define i1 @isnormal_f128(fp128 %x) nounwind {
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; CHECK-LABEL: isnormal_f128:
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; CHECK: # %bb.0:
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; CHECK-NEXT: stxv 34, -16(1)
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; CHECK-NEXT: li 4, -1
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; CHECK-NEXT: ld 3, -8(1)
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; CHECK-NEXT: rldic 4, 4, 48, 0
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; CHECK-NEXT: clrldi 3, 3, 1
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; CHECK-NEXT: add 3, 3, 4
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; CHECK-NEXT: li 4, 1
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; CHECK-NEXT: rldicl 3, 3, 15, 49
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; CHECK-NEXT: cmpldi 3, 16383
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; CHECK-NEXT: li 3, 0
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; CHECK-NEXT: isellt 3, 4, 3
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; CHECK-NEXT: blr
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%1 = call i1 @llvm.is.fpclass.f128(fp128 %x, i32 264) ; 0x108 = "normal"
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ret i1 %1
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}
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define i1 @issubnormal_float(float %x) nounwind {
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; CHECK-LABEL: issubnormal_float:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xscvdpspn 0, 1
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; CHECK-NEXT: lis 4, 127
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; CHECK-NEXT: ori 4, 4, 65535
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; CHECK-NEXT: mffprwz 3, 0
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; CHECK-NEXT: clrlwi 3, 3, 1
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; CHECK-NEXT: addi 3, 3, -1
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; CHECK-NEXT: cmplw 3, 4
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; CHECK-NEXT: li 3, 0
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; CHECK-NEXT: li 4, 1
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; CHECK-NEXT: isellt 3, 4, 3
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; CHECK-NEXT: blr
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%1 = call i1 @llvm.is.fpclass.f32(float %x, i32 144) ; 0x90 = "subnormal"
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ret i1 %1
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}
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define i1 @issubnormal_f128(fp128 %x) nounwind {
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; CHECK-LABEL: issubnormal_f128:
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; CHECK: # %bb.0:
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; CHECK-NEXT: stxv 34, -16(1)
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; CHECK-NEXT: li 5, -1
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; CHECK-NEXT: ld 4, -8(1)
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; CHECK-NEXT: ld 3, -16(1)
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; CHECK-NEXT: rldic 5, 5, 0, 16
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; CHECK-NEXT: clrldi 4, 4, 1
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; CHECK-NEXT: addic 3, 3, -1
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; CHECK-NEXT: addme 4, 4
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; CHECK-NEXT: cmpdi 1, 3, -1
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; CHECK-NEXT: li 3, 1
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; CHECK-NEXT: cmpld 4, 5
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; CHECK-NEXT: crandc 20, 0, 2
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; CHECK-NEXT: crandc 21, 2, 6
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; CHECK-NEXT: crnor 20, 21, 20
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; CHECK-NEXT: isel 3, 0, 3, 20
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; CHECK-NEXT: blr
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%1 = call i1 @llvm.is.fpclass.f128(fp128 %x, i32 144) ; 0x90 = "subnormal"
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ret i1 %1
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}
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define i1 @iszero_float(float %x) nounwind {
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; CHECK-LABEL: iszero_float:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xxlxor 0, 0, 0
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; CHECK-NEXT: li 3, 0
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; CHECK-NEXT: li 4, 1
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; CHECK-NEXT: fcmpu 0, 1, 0
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; CHECK-NEXT: iseleq 3, 4, 3
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; CHECK-NEXT: blr
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%1 = call i1 @llvm.is.fpclass.f32(float %x, i32 96) ; 0x60 = "zero"
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ret i1 %1
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}
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define i1 @iszero_f128(fp128 %x) nounwind {
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; CHECK-LABEL: iszero_f128:
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; CHECK: # %bb.0:
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; CHECK-NEXT: addis 3, 2, .LCPI18_0@toc@ha
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; CHECK-NEXT: li 4, 1
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; CHECK-NEXT: addi 3, 3, .LCPI18_0@toc@l
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; CHECK-NEXT: lxv 35, 0(3)
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; CHECK-NEXT: li 3, 0
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; CHECK-NEXT: xscmpuqp 0, 2, 3
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; CHECK-NEXT: iseleq 3, 4, 3
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; CHECK-NEXT: blr
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%1 = call i1 @llvm.is.fpclass.f128(fp128 %x, i32 96) ; 0x60 = "zero"
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ret i1 %1
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}
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declare i1 @llvm.is.fpclass.f32(float, i32)
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declare i1 @llvm.is.fpclass.f64(double, i32)
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declare i1 @llvm.is.fpclass.ppcf128(ppc_fp128, i32)
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declare i1 @llvm.is.fpclass.f128(fp128, i32)

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