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Revert "[Hexagon] Add instruction definitions for Hexagon v71, v71t, and v73"
This reverts commit 7665369. The commit caused: clang/include/clang/Basic/BuiltinsHexagonDep.def:1896:69: error: use of undeclared identifier 'HVXV73' TARGET_BUILTIN(__builtin_HEXAGON_V6_vadd_sf_bf, "V32iV16iV16i", "", HVXV73) when building `clang`.
1 parent 8003c1d commit 99f730c

25 files changed

+169
-5675
lines changed

‎clang/include/clang/Basic/BuiltinsHexagonDep.def

Lines changed: 0 additions & 33 deletions
Original file line numberDiff line numberDiff line change
@@ -1890,36 +1890,3 @@ TARGET_BUILTIN(__builtin_HEXAGON_V6_vasrvwuhsat, "V16iV32iV16i", "", HVXV69)
18901890
TARGET_BUILTIN(__builtin_HEXAGON_V6_vasrvwuhsat_128B, "V32iV64iV32i", "", HVXV69)
18911891
TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpyuhvs, "V16iV16iV16i", "", HVXV69)
18921892
TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpyuhvs_128B, "V32iV32iV32i", "", HVXV69)
1893-
1894-
// V73 HVX Instructions.
1895-
1896-
TARGET_BUILTIN(__builtin_HEXAGON_V6_vadd_sf_bf, "V32iV16iV16i", "", HVXV73)
1897-
TARGET_BUILTIN(__builtin_HEXAGON_V6_vadd_sf_bf_128B, "V64iV32iV32i", "", HVXV73)
1898-
TARGET_BUILTIN(__builtin_HEXAGON_V6_vconv_h_hf, "V16iV16i", "", HVXV73)
1899-
TARGET_BUILTIN(__builtin_HEXAGON_V6_vconv_h_hf_128B, "V32iV32i", "", HVXV73)
1900-
TARGET_BUILTIN(__builtin_HEXAGON_V6_vconv_hf_h, "V16iV16i", "", HVXV73)
1901-
TARGET_BUILTIN(__builtin_HEXAGON_V6_vconv_hf_h_128B, "V32iV32i", "", HVXV73)
1902-
TARGET_BUILTIN(__builtin_HEXAGON_V6_vconv_sf_w, "V16iV16i", "", HVXV73)
1903-
TARGET_BUILTIN(__builtin_HEXAGON_V6_vconv_sf_w_128B, "V32iV32i", "", HVXV73)
1904-
TARGET_BUILTIN(__builtin_HEXAGON_V6_vconv_w_sf, "V16iV16i", "", HVXV73)
1905-
TARGET_BUILTIN(__builtin_HEXAGON_V6_vconv_w_sf_128B, "V32iV32i", "", HVXV73)
1906-
TARGET_BUILTIN(__builtin_HEXAGON_V6_vcvt_bf_sf, "V16iV16iV16i", "", HVXV73)
1907-
TARGET_BUILTIN(__builtin_HEXAGON_V6_vcvt_bf_sf_128B, "V32iV32iV32i", "", HVXV73)
1908-
TARGET_BUILTIN(__builtin_HEXAGON_V6_vgtbf, "V64bV16iV16i", "", HVXV73)
1909-
TARGET_BUILTIN(__builtin_HEXAGON_V6_vgtbf_128B, "V128bV32iV32i", "", HVXV73)
1910-
TARGET_BUILTIN(__builtin_HEXAGON_V6_vgtbf_and, "V64bV64bV16iV16i", "", HVXV73)
1911-
TARGET_BUILTIN(__builtin_HEXAGON_V6_vgtbf_and_128B, "V128bV128bV32iV32i", "", HVXV73)
1912-
TARGET_BUILTIN(__builtin_HEXAGON_V6_vgtbf_or, "V64bV64bV16iV16i", "", HVXV73)
1913-
TARGET_BUILTIN(__builtin_HEXAGON_V6_vgtbf_or_128B, "V128bV128bV32iV32i", "", HVXV73)
1914-
TARGET_BUILTIN(__builtin_HEXAGON_V6_vgtbf_xor, "V64bV64bV16iV16i", "", HVXV73)
1915-
TARGET_BUILTIN(__builtin_HEXAGON_V6_vgtbf_xor_128B, "V128bV128bV32iV32i", "", HVXV73)
1916-
TARGET_BUILTIN(__builtin_HEXAGON_V6_vmax_bf, "V16iV16iV16i", "", HVXV73)
1917-
TARGET_BUILTIN(__builtin_HEXAGON_V6_vmax_bf_128B, "V32iV32iV32i", "", HVXV73)
1918-
TARGET_BUILTIN(__builtin_HEXAGON_V6_vmin_bf, "V16iV16iV16i", "", HVXV73)
1919-
TARGET_BUILTIN(__builtin_HEXAGON_V6_vmin_bf_128B, "V32iV32iV32i", "", HVXV73)
1920-
TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpy_sf_bf, "V32iV16iV16i", "", HVXV73)
1921-
TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpy_sf_bf_128B, "V64iV32iV32i", "", HVXV73)
1922-
TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpy_sf_bf_acc, "V32iV32iV16iV16i", "", HVXV73)
1923-
TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpy_sf_bf_acc_128B, "V64iV64iV32iV32i", "", HVXV73)
1924-
TARGET_BUILTIN(__builtin_HEXAGON_V6_vsub_sf_bf, "V32iV16iV16i", "", HVXV73)
1925-
TARGET_BUILTIN(__builtin_HEXAGON_V6_vsub_sf_bf_128B, "V64iV32iV32i", "", HVXV73)

‎llvm/include/llvm/IR/IntrinsicsHexagonDep.td

Lines changed: 3 additions & 95 deletions
Original file line numberDiff line numberDiff line change
@@ -316,7 +316,7 @@ class Hexagon_v32i32_v64i32_Intrinsic<string GCCIntSuffix,
316316
[llvm_v32i32_ty], [llvm_v64i32_ty],
317317
intr_properties>;
318318

319-
// tag : V6_lvsplatb
319+
// tag : V6_lvsplatw
320320
class Hexagon_v16i32_i32_Intrinsic<string GCCIntSuffix,
321321
list<IntrinsicProperty> intr_properties = [IntrNoMem]>
322322
: Hexagon_Intrinsic<GCCIntSuffix,
@@ -442,14 +442,14 @@ class Hexagon_v32i32_v32i32v32i32_Intrinsic<string GCCIntSuffix,
442442
[llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty],
443443
intr_properties>;
444444

445-
// tag : V6_vadd_sf_bf
445+
// tag : V6_vadd_sf_hf
446446
class Hexagon_v32i32_v16i32v16i32_Intrinsic<string GCCIntSuffix,
447447
list<IntrinsicProperty> intr_properties = [IntrNoMem]>
448448
: Hexagon_Intrinsic<GCCIntSuffix,
449449
[llvm_v32i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty],
450450
intr_properties>;
451451

452-
// tag : V6_vadd_sf_bf
452+
// tag : V6_vadd_sf_hf
453453
class Hexagon_v64i32_v32i32v32i32_Intrinsic<string GCCIntSuffix,
454454
list<IntrinsicProperty> intr_properties = [IntrNoMem]>
455455
: Hexagon_Intrinsic<GCCIntSuffix,
@@ -6613,95 +6613,3 @@ Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyuhvs">;
66136613
def int_hexagon_V6_vmpyuhvs_128B :
66146614
Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyuhvs_128B">;
66156615

6616-
// V73 HVX Instructions.
6617-
6618-
def int_hexagon_V6_vadd_sf_bf :
6619-
Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vadd_sf_bf">;
6620-
6621-
def int_hexagon_V6_vadd_sf_bf_128B :
6622-
Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vadd_sf_bf_128B">;
6623-
6624-
def int_hexagon_V6_vconv_h_hf :
6625-
Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vconv_h_hf">;
6626-
6627-
def int_hexagon_V6_vconv_h_hf_128B :
6628-
Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vconv_h_hf_128B">;
6629-
6630-
def int_hexagon_V6_vconv_hf_h :
6631-
Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vconv_hf_h">;
6632-
6633-
def int_hexagon_V6_vconv_hf_h_128B :
6634-
Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vconv_hf_h_128B">;
6635-
6636-
def int_hexagon_V6_vconv_sf_w :
6637-
Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vconv_sf_w">;
6638-
6639-
def int_hexagon_V6_vconv_sf_w_128B :
6640-
Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vconv_sf_w_128B">;
6641-
6642-
def int_hexagon_V6_vconv_w_sf :
6643-
Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vconv_w_sf">;
6644-
6645-
def int_hexagon_V6_vconv_w_sf_128B :
6646-
Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vconv_w_sf_128B">;
6647-
6648-
def int_hexagon_V6_vcvt_bf_sf :
6649-
Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vcvt_bf_sf">;
6650-
6651-
def int_hexagon_V6_vcvt_bf_sf_128B :
6652-
Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vcvt_bf_sf_128B">;
6653-
6654-
def int_hexagon_V6_vgtbf :
6655-
Hexagon_v64i1_v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtbf">;
6656-
6657-
def int_hexagon_V6_vgtbf_128B :
6658-
Hexagon_v128i1_v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtbf_128B">;
6659-
6660-
def int_hexagon_V6_vgtbf_and :
6661-
Hexagon_v64i1_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtbf_and">;
6662-
6663-
def int_hexagon_V6_vgtbf_and_128B :
6664-
Hexagon_v128i1_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtbf_and_128B">;
6665-
6666-
def int_hexagon_V6_vgtbf_or :
6667-
Hexagon_v64i1_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtbf_or">;
6668-
6669-
def int_hexagon_V6_vgtbf_or_128B :
6670-
Hexagon_v128i1_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtbf_or_128B">;
6671-
6672-
def int_hexagon_V6_vgtbf_xor :
6673-
Hexagon_v64i1_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtbf_xor">;
6674-
6675-
def int_hexagon_V6_vgtbf_xor_128B :
6676-
Hexagon_v128i1_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtbf_xor_128B">;
6677-
6678-
def int_hexagon_V6_vmax_bf :
6679-
Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmax_bf">;
6680-
6681-
def int_hexagon_V6_vmax_bf_128B :
6682-
Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmax_bf_128B">;
6683-
6684-
def int_hexagon_V6_vmin_bf :
6685-
Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmin_bf">;
6686-
6687-
def int_hexagon_V6_vmin_bf_128B :
6688-
Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmin_bf_128B">;
6689-
6690-
def int_hexagon_V6_vmpy_sf_bf :
6691-
Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpy_sf_bf">;
6692-
6693-
def int_hexagon_V6_vmpy_sf_bf_128B :
6694-
Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpy_sf_bf_128B">;
6695-
6696-
def int_hexagon_V6_vmpy_sf_bf_acc :
6697-
Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpy_sf_bf_acc">;
6698-
6699-
def int_hexagon_V6_vmpy_sf_bf_acc_128B :
6700-
Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpy_sf_bf_acc_128B">;
6701-
6702-
def int_hexagon_V6_vsub_sf_bf :
6703-
Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsub_sf_bf">;
6704-
6705-
def int_hexagon_V6_vsub_sf_bf_128B :
6706-
Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsub_sf_bf_128B">;
6707-

‎llvm/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp

Lines changed: 0 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -354,11 +354,6 @@ struct HexagonOperand : public MCParsedAsmOperand {
354354
return false;
355355
return Value == -1;
356356
}
357-
bool issgp10Const() const {
358-
if (!isReg())
359-
return false;
360-
return getReg() == Hexagon::SGP1_0;
361-
}
362357
bool iss11_0Imm() const {
363358
return CheckImmRange(11 + 26, 0, true, true, true);
364359
}
@@ -405,9 +400,6 @@ struct HexagonOperand : public MCParsedAsmOperand {
405400
void addn1ConstOperands(MCInst &Inst, unsigned N) const {
406401
addImmOperands(Inst, N);
407402
}
408-
void addsgp10ConstOperands(MCInst &Inst, unsigned N) const {
409-
addRegOperands(Inst, N);
410-
}
411403

412404
StringRef getToken() const {
413405
assert(Kind == Token && "Invalid access!");

‎llvm/lib/Target/Hexagon/Hexagon.td

Lines changed: 0 additions & 30 deletions
Original file line numberDiff line numberDiff line change
@@ -58,14 +58,6 @@ def ExtensionHVXV69: SubtargetFeature<"hvxv69", "HexagonHVXVersion",
5858
"Hexagon::ArchEnum::V69", "Hexagon HVX instructions",
5959
[ExtensionHVXV60, ExtensionHVXV62, ExtensionHVXV65, ExtensionHVXV66,
6060
ExtensionHVXV67, ExtensionHVXV68]>;
61-
def ExtensionHVXV71: SubtargetFeature<"hvxv71", "HexagonHVXVersion",
62-
"Hexagon::ArchEnum::V71", "Hexagon HVX instructions",
63-
[ExtensionHVXV60, ExtensionHVXV62, ExtensionHVXV65, ExtensionHVXV66,
64-
ExtensionHVXV67, ExtensionHVXV68, ExtensionHVXV69]>;
65-
def ExtensionHVXV73: SubtargetFeature<"hvxv73", "HexagonHVXVersion",
66-
"Hexagon::ArchEnum::V73", "Hexagon HVX instructions",
67-
[ExtensionHVXV60, ExtensionHVXV62, ExtensionHVXV65, ExtensionHVXV66,
68-
ExtensionHVXV67, ExtensionHVXV68, ExtensionHVXV69, ExtensionHVXV71]>;
6961

7062
def ExtensionHVX64B: SubtargetFeature<"hvx-length64b", "UseHVX64BOps",
7163
"true", "Hexagon HVX 64B instructions", [ExtensionHVX]>;
@@ -133,10 +125,6 @@ def UseHVXV68 : Predicate<"HST->useHVXV68Ops()">,
133125
AssemblerPredicate<(all_of ExtensionHVXV68)>;
134126
def UseHVXV69 : Predicate<"HST->useHVXV69Ops()">,
135127
AssemblerPredicate<(all_of ExtensionHVXV69)>;
136-
def UseHVXV71 : Predicate<"HST->useHVXV71Ops()">,
137-
AssemblerPredicate<(all_of ExtensionHVXV71)>;
138-
def UseHVXV73 : Predicate<"HST->useHVXV73Ops()">,
139-
AssemblerPredicate<(all_of ExtensionHVXV73)>;
140128
def UseAudio : Predicate<"HST->useAudioOps()">,
141129
AssemblerPredicate<(all_of ExtensionAudio)>;
142130
def UseZReg : Predicate<"HST->useZRegOps()">,
@@ -451,17 +439,6 @@ def : Proc<"hexagonv69", HexagonModelV69,
451439
FeatureCompound, FeatureDuplex, FeatureMemNoShuf, FeatureMemops,
452440
FeatureNVJ, FeatureNVS, FeaturePackets, FeatureSmallData,
453441
FeatureCabac]>;
454-
def : Proc<"hexagonv71", HexagonModelV71,
455-
[ArchV5, ArchV55, ArchV60, ArchV62, ArchV65, ArchV66, ArchV67,
456-
ArchV68, ArchV69, ArchV71,
457-
FeatureCompound, FeatureDuplex, FeatureMemNoShuf, FeatureMemops,
458-
FeatureNVJ, FeatureNVS, FeaturePackets, FeatureSmallData,
459-
FeatureCabac]>;
460-
def : Proc<"hexagonv73", HexagonModelV73,
461-
[ArchV5, ArchV55, ArchV60, ArchV62, ArchV65, ArchV66, ArchV67,
462-
ArchV68, ArchV69, ArchV71, ArchV73,
463-
FeatureCompound, FeatureDuplex, FeatureMemNoShuf, FeatureMemops,
464-
FeatureNVJ, FeatureNVS, FeaturePackets, FeatureSmallData]>;
465442
// Need to update the correct features for tiny core.
466443
// Disable NewValueJumps since the packetizer is unable to handle a packet with
467444
// a new value jump and another SLOT0 instruction.
@@ -471,13 +448,6 @@ def : Proc<"hexagonv67t", HexagonModelV67T,
471448
FeatureCompound, FeatureMemNoShuf, FeatureMemops,
472449
FeatureNVS, FeaturePackets, FeatureSmallData]>;
473450

474-
def : Proc<"hexagonv71t", HexagonModelV71T,
475-
[ArchV5, ArchV55, ArchV60, ArchV62, ArchV65, ArchV66, ArchV67,
476-
ArchV68, ArchV69, ArchV71,
477-
ProcTinyCore, ExtensionAudio,
478-
FeatureCompound, FeatureMemNoShuf, FeatureMemops,
479-
FeatureNVS, FeaturePackets, FeatureSmallData]>;
480-
481451
//===----------------------------------------------------------------------===//
482452
// Declare the target which we are implementing
483453
//===----------------------------------------------------------------------===//

‎llvm/lib/Target/Hexagon/HexagonDepArch.h

Lines changed: 4 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -5,6 +5,9 @@
55
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
66
//
77
//===----------------------------------------------------------------------===//
8+
// Automatically generated file, do not edit!
9+
//===----------------------------------------------------------------------===//
10+
811

912
#ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONDEPARCH_H
1013
#define LLVM_LIB_TARGET_HEXAGON_HEXAGONDEPARCH_H
@@ -13,21 +16,7 @@
1316

1417
namespace llvm {
1518
namespace Hexagon {
16-
enum class ArchEnum {
17-
NoArch,
18-
Generic,
19-
V5,
20-
V55,
21-
V60,
22-
V62,
23-
V65,
24-
V66,
25-
V67,
26-
V68,
27-
V69,
28-
V71,
29-
V73
30-
};
19+
enum class ArchEnum { NoArch, Generic, V5, V55, V60, V62, V65, V66, V67, V68, V69 };
3120

3221
inline Optional<Hexagon::ArchEnum> getCpu(StringRef CPU) {
3322
return StringSwitch<Optional<Hexagon::ArchEnum>>(CPU)
@@ -42,9 +31,6 @@ inline Optional<Hexagon::ArchEnum> getCpu(StringRef CPU) {
4231
.Case("hexagonv67t", Hexagon::ArchEnum::V67)
4332
.Case("hexagonv68", Hexagon::ArchEnum::V68)
4433
.Case("hexagonv69", Hexagon::ArchEnum::V69)
45-
.Case("hexagonv71", Hexagon::ArchEnum::V71)
46-
.Case("hexagonv71t", Hexagon::ArchEnum::V71)
47-
.Case("hexagonv73", Hexagon::ArchEnum::V73)
4834
.Default(None);
4935
}
5036
} // namespace Hexagon

‎llvm/lib/Target/Hexagon/HexagonDepArch.td

Lines changed: 0 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -26,7 +26,3 @@ def ArchV68: SubtargetFeature<"v68", "HexagonArchVersion", "Hexagon::ArchEnum::V
2626
def HasV68 : Predicate<"HST->hasV68Ops()">, AssemblerPredicate<(all_of ArchV68)>;
2727
def ArchV69: SubtargetFeature<"v69", "HexagonArchVersion", "Hexagon::ArchEnum::V69", "Enable Hexagon V69 architecture">;
2828
def HasV69 : Predicate<"HST->hasV69Ops()">, AssemblerPredicate<(all_of ArchV69)>;
29-
def ArchV71: SubtargetFeature<"v71", "HexagonArchVersion", "Hexagon::ArchEnum::V71", "Enable Hexagon V71 architecture">;
30-
def HasV71 : Predicate<"HST->hasV71Ops()">, AssemblerPredicate<(all_of ArchV71)>;
31-
def ArchV73: SubtargetFeature<"v73", "HexagonArchVersion", "Hexagon::ArchEnum::V73", "Enable Hexagon V73 architecture">;
32-
def HasV73 : Predicate<"HST->hasV73Ops()">, AssemblerPredicate<(all_of ArchV73)>;

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