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| 1 | +# RUN: llc -mtriple=aarch64-linux-gnu -verify-machineinstrs -run-pass=aarch64-ldst-opt %s -o - | FileCheck %s |
| 2 | +# |
| 3 | +# When the AArch64 Load Store Optimization pass tries to convert load instructions |
| 4 | +# into a ldp instruction, and when the base register of the second ldr instruction |
| 5 | +# has been modified in between these two ldr instructions, the conversion should not |
| 6 | +# occur. |
| 7 | +# |
| 8 | +# For example, for the following pattern: |
| 9 | +# ldr x9 [x10] |
| 10 | +# ldr x10 [x8] |
| 11 | +# ldr x10 [x10, 8], |
| 12 | +# the first and third ldr instructions cannot be converted to ldp x9, x10, [x10]. |
| 13 | +# |
| 14 | +# CHECK-LABEL: name: ldr-modified-baseReg-no-ldp1 |
| 15 | +# CHECK-NOT: LDP |
| 16 | +# CHECK: $x9 = LDRXui $x10, 1 :: (load 8) |
| 17 | +# CHECK: $x10 = LDURXi $x8, 1 :: (load 8) |
| 18 | +# CHECK: $x10 = LDRXui $x10, 0 :: (load 8) |
| 19 | +# CHECK: RET |
| 20 | +--- |
| 21 | +name: ldr-modified-baseReg-no-ldp1 |
| 22 | +tracksRegLiveness: true |
| 23 | +body: | |
| 24 | + bb.0: |
| 25 | + liveins: $x8, $x10 |
| 26 | +
|
| 27 | + $x9 = LDRXui $x10, 1 :: (load 8) |
| 28 | + $x10 = LDURXi $x8, 1 :: (load 8) |
| 29 | + $x10 = LDRXui $x10, 0 :: (load 8) |
| 30 | + RET undef $lr, implicit undef $w0 |
| 31 | +... |
| 32 | + |
| 33 | +# CHECK-LABEL: name: str-modified-baseReg-no-stp1 |
| 34 | +# CHECK-NOT: STP |
| 35 | +# CHECK: STRXui $x9, $x10, 1 :: (store 8) |
| 36 | +# CHECK: $x10 = LDRXui $x8, 0 :: (load 8) |
| 37 | +# CHECK: STRXui $x10, $x10, 0 :: (store 8) |
| 38 | +# CHECK: RET |
| 39 | +--- |
| 40 | +name: str-modified-baseReg-no-stp1 |
| 41 | +tracksRegLiveness: true |
| 42 | +body: | |
| 43 | + bb.0: |
| 44 | + liveins: $x9, $x8, $x10 |
| 45 | +
|
| 46 | + STRXui $x9, $x10, 1 :: (store 8) |
| 47 | + $x10 = LDRXui $x8, 0 :: (load 8) |
| 48 | + STRXui $x10, $x10, 0 :: (store 8) |
| 49 | + RET undef $lr, implicit undef $w0 |
| 50 | +... |
| 51 | + |
| 52 | +# CHECK-LABEL: name: ldr-modified-baseReg-no-ldp2 |
| 53 | +# CHECK-NOT: LDP |
| 54 | +# CHECK: $x9 = LDRXui $x10, 1 :: (load 8) |
| 55 | +# CHECK: $x10 = MOVi64imm 13 |
| 56 | +# CHECK: $x11 = LDRXui $x10, 0 :: (load 8) |
| 57 | +# CHECK: RET |
| 58 | +--- |
| 59 | +name: ldr-modified-baseReg-no-ldp2 |
| 60 | +tracksRegLiveness: true |
| 61 | +body: | |
| 62 | + bb.0: |
| 63 | + liveins: $x8, $x10 |
| 64 | +
|
| 65 | + $x9 = LDRXui $x10, 1 :: (load 8) |
| 66 | + $x10 = MOVi64imm 13 |
| 67 | + $x11 = LDRXui $x10, 0 :: (load 8) |
| 68 | + RET undef $lr, implicit undef $w0 |
| 69 | +... |
| 70 | + |
| 71 | +# CHECK-LABEL: name: ldr-modified-baseReg-no-ldp3 |
| 72 | +# CHECK-NOT: LDP |
| 73 | +# CHECK: $x9 = LDRXui $x10, 1 :: (load 8) |
| 74 | +# CHECK: $x10 = ADDXri $x8, $x11, 0 |
| 75 | +# CHECK: $x12 = LDRXui $x10, 0 :: (load 8) |
| 76 | +# CHECK: RET |
| 77 | +--- |
| 78 | +name: ldr-modified-baseReg-no-ldp3 |
| 79 | +tracksRegLiveness: true |
| 80 | +body: | |
| 81 | + bb.0: |
| 82 | + liveins: $x8, $x10, $x11 |
| 83 | +
|
| 84 | + $x9 = LDRXui $x10, 1 :: (load 8) |
| 85 | + $x10 = ADDXri $x8, $x11, 0 |
| 86 | + $x12 = LDRXui $x10, 0 :: (load 8) |
| 87 | + RET undef $lr, implicit undef $w0 |
| 88 | +... |
| 89 | + |
| 90 | +# CHECK-LABEL: name: ldr-modified-baseAddr-convert-to-ldp |
| 91 | +# CHECK: $x12, $x9 = LDPXi $x10, 0 :: (load 8) |
| 92 | +# CHECK: STRXui $x11, $x10, 1 :: (store 8) |
| 93 | +# CHECK: RET |
| 94 | +--- |
| 95 | +name: ldr-modified-baseAddr-convert-to-ldp |
| 96 | +tracksRegLiveness: true |
| 97 | +body: | |
| 98 | + bb.0: |
| 99 | + liveins: $x8, $x10, $x11 |
| 100 | +
|
| 101 | + $x9 = LDRXui $x10, 1 :: (load 8) |
| 102 | + STRXui $x11, $x10, 1 :: (store 8) |
| 103 | + $x12 = LDRXui $x10, 0 :: (load 8) |
| 104 | + RET undef $lr, implicit undef $w0 |
| 105 | +... |
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