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LuoYuankeLuoYuanke
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[X86] Pre-checkin test case for combining const operand to VNNI
instruction.
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‎llvm/test/CodeGen/X86/dpbusd_const.ll

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avxvnni | FileCheck %s --check-prefixes=ALL,AVXVNNI
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512vnni | FileCheck %s --check-prefixes=ALL,AVX512,AVX512VNNI
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512vnni -mattr=+avx512vl | FileCheck %s --check-prefixes=ALL,AVX512,AVX512VLVNNI
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define i32 @mul_4xi8_zc_exceed(<4 x i8> %a, i32 %c) {
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; ALL-LABEL: mul_4xi8_zc_exceed:
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; ALL: # %bb.0: # %entry
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; ALL-NEXT: vpmovzxbd {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero
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; ALL-NEXT: vpmaddwd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
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; ALL-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
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; ALL-NEXT: vpaddd %xmm1, %xmm0, %xmm0
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; ALL-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,1,1]
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; ALL-NEXT: vpaddd %xmm1, %xmm0, %xmm0
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; ALL-NEXT: vmovd %xmm0, %eax
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; ALL-NEXT: addl %edi, %eax
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; ALL-NEXT: retq
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entry:
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%0 = zext <4 x i8> %a to <4 x i32>
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%1 = mul nsw <4 x i32> %0, <i32 0, i32 1, i32 2, i32 128>
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%2 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %1)
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%op.extra = add nsw i32 %2, %c
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ret i32 %op.extra
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}
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define i32 @mul_4xi8_zc(<4 x i8> %a, i32 %c) {
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; ALL-LABEL: mul_4xi8_zc:
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; ALL: # %bb.0: # %entry
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; ALL-NEXT: vpmovzxbd {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero
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; ALL-NEXT: vpmaddwd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
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; ALL-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
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; ALL-NEXT: vpaddd %xmm1, %xmm0, %xmm0
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; ALL-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,1,1]
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; ALL-NEXT: vpaddd %xmm1, %xmm0, %xmm0
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; ALL-NEXT: vmovd %xmm0, %eax
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; ALL-NEXT: addl %edi, %eax
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; ALL-NEXT: retq
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entry:
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%0 = zext <4 x i8> %a to <4 x i32>
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%1 = mul nsw <4 x i32> %0, <i32 0, i32 1, i32 2, i32 127>
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%2 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %1)
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%op.extra = add nsw i32 %2, %c
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ret i32 %op.extra
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}
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define i32 @mul_4xi4_cz(<4 x i4> %a, i32 %c) {
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; AVXVNNI-LABEL: mul_4xi4_cz:
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; AVXVNNI: # %bb.0: # %entry
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; AVXVNNI-NEXT: vpbroadcastd {{.*#+}} xmm1 = [15,15,15,15]
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; AVXVNNI-NEXT: vpand %xmm1, %xmm0, %xmm0
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; AVXVNNI-NEXT: vpmaddwd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
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; AVXVNNI-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
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; AVXVNNI-NEXT: vpaddd %xmm1, %xmm0, %xmm0
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; AVXVNNI-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,1,1]
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; AVXVNNI-NEXT: vpaddd %xmm1, %xmm0, %xmm0
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; AVXVNNI-NEXT: vmovd %xmm0, %eax
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; AVXVNNI-NEXT: addl %edi, %eax
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; AVXVNNI-NEXT: retq
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;
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; AVX512VNNI-LABEL: mul_4xi4_cz:
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; AVX512VNNI: # %bb.0: # %entry
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; AVX512VNNI-NEXT: vpbroadcastd {{.*#+}} xmm1 = [15,15,15,15]
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; AVX512VNNI-NEXT: vpand %xmm1, %xmm0, %xmm0
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; AVX512VNNI-NEXT: vpmaddwd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
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; AVX512VNNI-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
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; AVX512VNNI-NEXT: vpaddd %xmm1, %xmm0, %xmm0
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; AVX512VNNI-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,1,1]
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; AVX512VNNI-NEXT: vpaddd %xmm1, %xmm0, %xmm0
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; AVX512VNNI-NEXT: vmovd %xmm0, %eax
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; AVX512VNNI-NEXT: addl %edi, %eax
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; AVX512VNNI-NEXT: retq
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;
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; AVX512VLVNNI-LABEL: mul_4xi4_cz:
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; AVX512VLVNNI: # %bb.0: # %entry
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; AVX512VLVNNI-NEXT: vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm0
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; AVX512VLVNNI-NEXT: vpmaddwd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
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; AVX512VLVNNI-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
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; AVX512VLVNNI-NEXT: vpaddd %xmm1, %xmm0, %xmm0
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; AVX512VLVNNI-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,1,1]
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; AVX512VLVNNI-NEXT: vpaddd %xmm1, %xmm0, %xmm0
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; AVX512VLVNNI-NEXT: vmovd %xmm0, %eax
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; AVX512VLVNNI-NEXT: addl %edi, %eax
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; AVX512VLVNNI-NEXT: retq
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entry:
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%0 = zext <4 x i4> %a to <4 x i32>
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%1 = mul nsw <4 x i32> <i32 0, i32 1, i32 2, i32 127>, %0
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%2 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %1)
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%op.extra = add nsw i32 %2, %c
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ret i32 %op.extra
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}
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define i32 @mul_4xi8_cs(<4 x i8> %a, i32 %c) {
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; ALL-LABEL: mul_4xi8_cs:
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; ALL: # %bb.0: # %entry
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; ALL-NEXT: vpmovsxbd %xmm0, %xmm0
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; ALL-NEXT: vpmaddwd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
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; ALL-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
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; ALL-NEXT: vpaddd %xmm1, %xmm0, %xmm0
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; ALL-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,1,1]
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; ALL-NEXT: vpaddd %xmm1, %xmm0, %xmm0
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; ALL-NEXT: vmovd %xmm0, %eax
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; ALL-NEXT: addl %edi, %eax
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; ALL-NEXT: retq
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entry:
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%0 = sext <4 x i8> %a to <4 x i32>
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%1 = mul nsw <4 x i32> <i32 0, i32 1, i32 2, i32 255>, %0
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%2 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %1)
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%op.extra = add nsw i32 %2, %c
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ret i32 %op.extra
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}
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define i32 @mul_4xi8_cs_exceed(<4 x i8> %a, i32 %c) {
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; ALL-LABEL: mul_4xi8_cs_exceed:
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; ALL: # %bb.0: # %entry
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; ALL-NEXT: vpmovsxbd %xmm0, %xmm0
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; ALL-NEXT: vpmaddwd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
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; ALL-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
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; ALL-NEXT: vpaddd %xmm1, %xmm0, %xmm0
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; ALL-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,1,1]
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; ALL-NEXT: vpaddd %xmm1, %xmm0, %xmm0
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; ALL-NEXT: vmovd %xmm0, %eax
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; ALL-NEXT: addl %edi, %eax
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; ALL-NEXT: retq
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entry:
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%0 = sext <4 x i8> %a to <4 x i32>
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%1 = mul nsw <4 x i32> <i32 0, i32 1, i32 2, i32 256>, %0
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%2 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %1)
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%op.extra = add nsw i32 %2, %c
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ret i32 %op.extra
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}
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define i32 @mul_16xi8_zc(<16 x i8> %a, i32 %c) {
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; AVXVNNI-LABEL: mul_16xi8_zc:
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; AVXVNNI: # %bb.0: # %entry
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; AVXVNNI-NEXT: vpmovzxbw {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero,xmm0[8],zero,xmm0[9],zero,xmm0[10],zero,xmm0[11],zero,xmm0[12],zero,xmm0[13],zero,xmm0[14],zero,xmm0[15],zero
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; AVXVNNI-NEXT: vpmaddwd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
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; AVXVNNI-NEXT: vextracti128 $1, %ymm0, %xmm1
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; AVXVNNI-NEXT: vpaddd %xmm1, %xmm0, %xmm0
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; AVXVNNI-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
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; AVXVNNI-NEXT: vpaddd %xmm1, %xmm0, %xmm0
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; AVXVNNI-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,1,1]
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; AVXVNNI-NEXT: vpaddd %xmm1, %xmm0, %xmm0
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; AVXVNNI-NEXT: vmovd %xmm0, %eax
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; AVXVNNI-NEXT: addl %edi, %eax
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; AVXVNNI-NEXT: vzeroupper
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; AVXVNNI-NEXT: retq
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;
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; AVX512-LABEL: mul_16xi8_zc:
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; AVX512: # %bb.0: # %entry
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; AVX512-NEXT: vpmovzxbw {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero,xmm0[8],zero,xmm0[9],zero,xmm0[10],zero,xmm0[11],zero,xmm0[12],zero,xmm0[13],zero,xmm0[14],zero,xmm0[15],zero
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; AVX512-NEXT: vpmaddwd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
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; AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1
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; AVX512-NEXT: vpaddd %ymm1, %ymm0, %ymm0
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; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
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; AVX512-NEXT: vpaddd %xmm1, %xmm0, %xmm0
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; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,1,1]
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; AVX512-NEXT: vpaddd %xmm1, %xmm0, %xmm0
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; AVX512-NEXT: vmovd %xmm0, %eax
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; AVX512-NEXT: addl %edi, %eax
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; AVX512-NEXT: vzeroupper
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; AVX512-NEXT: retq
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entry:
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%0 = zext <16 x i8> %a to <16 x i32>
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%1 = mul nsw <16 x i32> %0, <i32 0, i32 1, i32 2, i32 64, i32 0, i32 1, i32 2, i32 64, i32 0, i32 1, i32 2, i32 64, i32 0, i32 1, i32 2, i32 64>
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%2 = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %1)
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%op.extra = add nsw i32 %2, %c
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ret i32 %op.extra
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}
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define i32 @mul_32xi8_zc(<32 x i8> %a, i32 %c) {
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; AVXVNNI-LABEL: mul_32xi8_zc:
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; AVXVNNI: # %bb.0: # %entry
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; AVXVNNI-NEXT: vpmovzxbw {{.*#+}} ymm1 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero,xmm0[8],zero,xmm0[9],zero,xmm0[10],zero,xmm0[11],zero,xmm0[12],zero,xmm0[13],zero,xmm0[14],zero,xmm0[15],zero
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; AVXVNNI-NEXT: vpbroadcastq {{.*#+}} ymm2 = [18014407099482112,18014407099482112,18014407099482112,18014407099482112]
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; AVXVNNI-NEXT: vpmaddwd %ymm2, %ymm1, %ymm1
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; AVXVNNI-NEXT: vextracti128 $1, %ymm0, %xmm0
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; AVXVNNI-NEXT: vpmovzxbw {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero,xmm0[8],zero,xmm0[9],zero,xmm0[10],zero,xmm0[11],zero,xmm0[12],zero,xmm0[13],zero,xmm0[14],zero,xmm0[15],zero
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; AVXVNNI-NEXT: {vex} vpdpwssd %ymm2, %ymm0, %ymm1
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; AVXVNNI-NEXT: vextracti128 $1, %ymm1, %xmm0
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; AVXVNNI-NEXT: vpaddd %xmm0, %xmm1, %xmm0
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; AVXVNNI-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
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; AVXVNNI-NEXT: vpaddd %xmm1, %xmm0, %xmm0
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; AVXVNNI-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,1,1]
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; AVXVNNI-NEXT: vpaddd %xmm1, %xmm0, %xmm0
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; AVXVNNI-NEXT: vmovd %xmm0, %eax
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; AVXVNNI-NEXT: addl %edi, %eax
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; AVXVNNI-NEXT: vzeroupper
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; AVXVNNI-NEXT: retq
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;
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; AVX512-LABEL: mul_32xi8_zc:
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; AVX512: # %bb.0: # %entry
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; AVX512-NEXT: vpmovzxbw {{.*#+}} ymm1 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero,xmm0[8],zero,xmm0[9],zero,xmm0[10],zero,xmm0[11],zero,xmm0[12],zero,xmm0[13],zero,xmm0[14],zero,xmm0[15],zero
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; AVX512-NEXT: vpbroadcastq {{.*#+}} ymm2 = [18014407099482112,18014407099482112,18014407099482112,18014407099482112]
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; AVX512-NEXT: vpmaddwd %ymm2, %ymm1, %ymm1
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; AVX512-NEXT: vextracti128 $1, %ymm0, %xmm0
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; AVX512-NEXT: vpmovzxbw {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero,xmm0[8],zero,xmm0[9],zero,xmm0[10],zero,xmm0[11],zero,xmm0[12],zero,xmm0[13],zero,xmm0[14],zero,xmm0[15],zero
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; AVX512-NEXT: vpmaddwd %ymm2, %ymm0, %ymm0
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; AVX512-NEXT: vextracti128 $1, %ymm0, %xmm2
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; AVX512-NEXT: vextracti128 $1, %ymm1, %xmm3
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; AVX512-NEXT: vpaddd %xmm2, %xmm3, %xmm2
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; AVX512-NEXT: vpaddd %xmm2, %xmm0, %xmm0
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; AVX512-NEXT: vpaddd %xmm0, %xmm1, %xmm0
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; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
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; AVX512-NEXT: vpaddd %xmm1, %xmm0, %xmm0
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; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,1,1]
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; AVX512-NEXT: vpaddd %xmm1, %xmm0, %xmm0
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; AVX512-NEXT: vmovd %xmm0, %eax
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; AVX512-NEXT: addl %edi, %eax
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; AVX512-NEXT: vzeroupper
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; AVX512-NEXT: retq
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entry:
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%0 = zext <32 x i8> %a to <32 x i32>
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%1 = mul nsw <32 x i32> %0, <i32 0, i32 1, i32 2, i32 64, i32 0, i32 1, i32 2, i32 64, i32 0, i32 1, i32 2, i32 64, i32 0, i32 1, i32 2, i32 64, i32 0, i32 1, i32 2, i32 64, i32 0, i32 1, i32 2, i32 64, i32 0, i32 1, i32 2, i32 64, i32 0, i32 1, i32 2, i32 64>
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%2 = call i32 @llvm.vector.reduce.add.v32i32(<32 x i32> %1)
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%op.extra = add nsw i32 %2, %c
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ret i32 %op.extra
217+
}
218+
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define i32 @mul_64xi8_zc(<64 x i8> %a, i32 %c) {
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; AVXVNNI-LABEL: mul_64xi8_zc:
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; AVXVNNI: # %bb.0: # %entry
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; AVXVNNI-NEXT: vpmovzxbw {{.*#+}} ymm2 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero,xmm0[8],zero,xmm0[9],zero,xmm0[10],zero,xmm0[11],zero,xmm0[12],zero,xmm0[13],zero,xmm0[14],zero,xmm0[15],zero
223+
; AVXVNNI-NEXT: vpbroadcastq {{.*#+}} ymm3 = [18014407099482112,18014407099482112,18014407099482112,18014407099482112]
224+
; AVXVNNI-NEXT: vpmaddwd %ymm3, %ymm2, %ymm2
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; AVXVNNI-NEXT: vextracti128 $1, %ymm0, %xmm0
226+
; AVXVNNI-NEXT: vpmovzxbw {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero,xmm0[8],zero,xmm0[9],zero,xmm0[10],zero,xmm0[11],zero,xmm0[12],zero,xmm0[13],zero,xmm0[14],zero,xmm0[15],zero
227+
; AVXVNNI-NEXT: vpmaddwd %ymm3, %ymm0, %ymm0
228+
; AVXVNNI-NEXT: vpmovzxbw {{.*#+}} ymm4 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero,xmm1[8],zero,xmm1[9],zero,xmm1[10],zero,xmm1[11],zero,xmm1[12],zero,xmm1[13],zero,xmm1[14],zero,xmm1[15],zero
229+
; AVXVNNI-NEXT: vextracti128 $1, %ymm1, %xmm1
230+
; AVXVNNI-NEXT: vpmovzxbw {{.*#+}} ymm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero,xmm1[8],zero,xmm1[9],zero,xmm1[10],zero,xmm1[11],zero,xmm1[12],zero,xmm1[13],zero,xmm1[14],zero,xmm1[15],zero
231+
; AVXVNNI-NEXT: {vex} vpdpwssd %ymm3, %ymm1, %ymm0
232+
; AVXVNNI-NEXT: {vex} vpdpwssd %ymm3, %ymm4, %ymm2
233+
; AVXVNNI-NEXT: vpaddd %ymm0, %ymm2, %ymm0
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; AVXVNNI-NEXT: vextracti128 $1, %ymm0, %xmm1
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; AVXVNNI-NEXT: vpaddd %xmm1, %xmm0, %xmm0
236+
; AVXVNNI-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
237+
; AVXVNNI-NEXT: vpaddd %xmm1, %xmm0, %xmm0
238+
; AVXVNNI-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,1,1]
239+
; AVXVNNI-NEXT: vpaddd %xmm1, %xmm0, %xmm0
240+
; AVXVNNI-NEXT: vmovd %xmm0, %eax
241+
; AVXVNNI-NEXT: addl %edi, %eax
242+
; AVXVNNI-NEXT: vzeroupper
243+
; AVXVNNI-NEXT: retq
244+
;
245+
; AVX512-LABEL: mul_64xi8_zc:
246+
; AVX512: # %bb.0: # %entry
247+
; AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1
248+
; AVX512-NEXT: vpmovzxbw {{.*#+}} ymm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero,xmm1[8],zero,xmm1[9],zero,xmm1[10],zero,xmm1[11],zero,xmm1[12],zero,xmm1[13],zero,xmm1[14],zero,xmm1[15],zero
249+
; AVX512-NEXT: vpbroadcastq {{.*#+}} ymm2 = [18014407099482112,18014407099482112,18014407099482112,18014407099482112]
250+
; AVX512-NEXT: vpmaddwd %ymm2, %ymm1, %ymm1
251+
; AVX512-NEXT: vpmovzxbw {{.*#+}} ymm3 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero,xmm0[8],zero,xmm0[9],zero,xmm0[10],zero,xmm0[11],zero,xmm0[12],zero,xmm0[13],zero,xmm0[14],zero,xmm0[15],zero
252+
; AVX512-NEXT: vpmaddwd %ymm2, %ymm3, %ymm3
253+
; AVX512-NEXT: vinserti64x4 $1, %ymm1, %zmm3, %zmm3
254+
; AVX512-NEXT: vextracti64x4 $1, %zmm0, %ymm0
255+
; AVX512-NEXT: vextracti128 $1, %ymm0, %xmm4
256+
; AVX512-NEXT: vpmovzxbw {{.*#+}} ymm4 = xmm4[0],zero,xmm4[1],zero,xmm4[2],zero,xmm4[3],zero,xmm4[4],zero,xmm4[5],zero,xmm4[6],zero,xmm4[7],zero,xmm4[8],zero,xmm4[9],zero,xmm4[10],zero,xmm4[11],zero,xmm4[12],zero,xmm4[13],zero,xmm4[14],zero,xmm4[15],zero
257+
; AVX512-NEXT: vpmaddwd %ymm2, %ymm4, %ymm4
258+
; AVX512-NEXT: vpmovzxbw {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero,xmm0[8],zero,xmm0[9],zero,xmm0[10],zero,xmm0[11],zero,xmm0[12],zero,xmm0[13],zero,xmm0[14],zero,xmm0[15],zero
259+
; AVX512-NEXT: vpmaddwd %ymm2, %ymm0, %ymm0
260+
; AVX512-NEXT: vinserti64x4 $1, %ymm4, %zmm0, %zmm0
261+
; AVX512-NEXT: vpaddd %ymm4, %ymm1, %ymm1
262+
; AVX512-NEXT: vpaddd %zmm1, %zmm0, %zmm0
263+
; AVX512-NEXT: vpaddd %zmm0, %zmm3, %zmm0
264+
; AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1
265+
; AVX512-NEXT: vpaddd %xmm1, %xmm0, %xmm0
266+
; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
267+
; AVX512-NEXT: vpaddd %xmm1, %xmm0, %xmm0
268+
; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,1,1]
269+
; AVX512-NEXT: vpaddd %xmm1, %xmm0, %xmm0
270+
; AVX512-NEXT: vmovd %xmm0, %eax
271+
; AVX512-NEXT: addl %edi, %eax
272+
; AVX512-NEXT: vzeroupper
273+
; AVX512-NEXT: retq
274+
entry:
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%0 = zext <64 x i8> %a to <64 x i32>
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%1 = mul nsw <64 x i32> %0, <i32 0, i32 1, i32 2, i32 64, i32 0, i32 1, i32 2, i32 64, i32 0, i32 1, i32 2, i32 64, i32 0, i32 1, i32 2, i32 64, i32 0, i32 1, i32 2, i32 64, i32 0, i32 1, i32 2, i32 64, i32 0, i32 1, i32 2, i32 64, i32 0, i32 1, i32 2, i32 64, i32 0, i32 1, i32 2, i32 64, i32 0, i32 1, i32 2, i32 64, i32 0, i32 1, i32 2, i32 64, i32 0, i32 1, i32 2, i32 64, i32 0, i32 1, i32 2, i32 64, i32 0, i32 1, i32 2, i32 64, i32 0, i32 1, i32 2, i32 64, i32 0, i32 1, i32 2, i32 64>
277+
%2 = call i32 @llvm.vector.reduce.add.v64i32(<64 x i32> %1)
278+
%op.extra = add nsw i32 %2, %c
279+
ret i32 %op.extra
280+
}
281+
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declare i32 @llvm.vector.reduce.add.v4i32(<4 x i32>)
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declare i32 @llvm.vector.reduce.add.v16i32(<16 x i32>)
284+
declare i32 @llvm.vector.reduce.add.v32i32(<32 x i32>)
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declare i32 @llvm.vector.reduce.add.v64i32(<64 x i32>)

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