Skip to content

Commit 847bb26

Browse files
jayfoadjayfoad
committed
[AMDGPU] Regenerate some MIR checks
1 parent ccaaeca commit 847bb26

File tree

2 files changed

+88
-75
lines changed

2 files changed

+88
-75
lines changed

‎llvm/test/CodeGen/AMDGPU/GlobalISel/combine-itofp.mir

Lines changed: 82 additions & 70 deletions
Original file line numberDiff line numberDiff line change
@@ -10,11 +10,12 @@ body: |
1010
1111
; CHECK-LABEL: name: uitofp_char_to_f32
1212
; CHECK: liveins: $vgpr0
13-
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
14-
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
15-
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
16-
; CHECK: [[AMDGPU_CVT_F32_UBYTE0_:%[0-9]+]]:_(s32) = G_AMDGPU_CVT_F32_UBYTE0 [[AND]]
17-
; CHECK: $vgpr0 = COPY [[AMDGPU_CVT_F32_UBYTE0_]](s32)
13+
; CHECK-NEXT: {{ $}}
14+
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
15+
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
16+
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
17+
; CHECK-NEXT: [[AMDGPU_CVT_F32_UBYTE0_:%[0-9]+]]:_(s32) = G_AMDGPU_CVT_F32_UBYTE0 [[AND]]
18+
; CHECK-NEXT: $vgpr0 = COPY [[AMDGPU_CVT_F32_UBYTE0_]](s32)
1819
%0:_(s32) = COPY $vgpr0
1920
%1:_(s32) = G_CONSTANT i32 255
2021
%2:_(s32) = G_AND %0, %1
@@ -31,11 +32,12 @@ body: |
3132
3233
; CHECK-LABEL: name: uitofp_too_many_bits_to_f32
3334
; CHECK: liveins: $vgpr0
34-
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
35-
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 256
36-
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
37-
; CHECK: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[AND]](s32)
38-
; CHECK: $vgpr0 = COPY [[UITOFP]](s32)
35+
; CHECK-NEXT: {{ $}}
36+
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
37+
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 256
38+
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
39+
; CHECK-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[AND]](s32)
40+
; CHECK-NEXT: $vgpr0 = COPY [[UITOFP]](s32)
3941
%0:_(s32) = COPY $vgpr0
4042
%1:_(s32) = G_CONSTANT i32 256
4143
%2:_(s32) = G_AND %0, %1
@@ -52,11 +54,12 @@ body: |
5254
5355
; CHECK-LABEL: name: sitofp_char_to_f32
5456
; CHECK: liveins: $vgpr0
55-
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
56-
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
57-
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
58-
; CHECK: [[AMDGPU_CVT_F32_UBYTE0_:%[0-9]+]]:_(s32) = G_AMDGPU_CVT_F32_UBYTE0 [[AND]]
59-
; CHECK: $vgpr0 = COPY [[AMDGPU_CVT_F32_UBYTE0_]](s32)
57+
; CHECK-NEXT: {{ $}}
58+
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
59+
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
60+
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
61+
; CHECK-NEXT: [[AMDGPU_CVT_F32_UBYTE0_:%[0-9]+]]:_(s32) = G_AMDGPU_CVT_F32_UBYTE0 [[AND]]
62+
; CHECK-NEXT: $vgpr0 = COPY [[AMDGPU_CVT_F32_UBYTE0_]](s32)
6063
%0:_(s32) = COPY $vgpr0
6164
%1:_(s32) = G_CONSTANT i32 255
6265
%2:_(s32) = G_AND %0, %1
@@ -73,11 +76,12 @@ body: |
7376
7477
; CHECK-LABEL: name: sitofp_bits127_to_f32
7578
; CHECK: liveins: $vgpr0
76-
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
77-
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 127
78-
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
79-
; CHECK: [[AMDGPU_CVT_F32_UBYTE0_:%[0-9]+]]:_(s32) = G_AMDGPU_CVT_F32_UBYTE0 [[AND]]
80-
; CHECK: $vgpr0 = COPY [[AMDGPU_CVT_F32_UBYTE0_]](s32)
79+
; CHECK-NEXT: {{ $}}
80+
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
81+
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 127
82+
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
83+
; CHECK-NEXT: [[AMDGPU_CVT_F32_UBYTE0_:%[0-9]+]]:_(s32) = G_AMDGPU_CVT_F32_UBYTE0 [[AND]]
84+
; CHECK-NEXT: $vgpr0 = COPY [[AMDGPU_CVT_F32_UBYTE0_]](s32)
8185
%0:_(s32) = COPY $vgpr0
8286
%1:_(s32) = G_CONSTANT i32 127
8387
%2:_(s32) = G_AND %0, %1
@@ -94,11 +98,12 @@ body: |
9498
9599
; CHECK-LABEL: name: sitofp_bits128_to_f32
96100
; CHECK: liveins: $vgpr0
97-
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
98-
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 128
99-
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
100-
; CHECK: [[AMDGPU_CVT_F32_UBYTE0_:%[0-9]+]]:_(s32) = G_AMDGPU_CVT_F32_UBYTE0 [[AND]]
101-
; CHECK: $vgpr0 = COPY [[AMDGPU_CVT_F32_UBYTE0_]](s32)
101+
; CHECK-NEXT: {{ $}}
102+
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
103+
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 128
104+
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
105+
; CHECK-NEXT: [[AMDGPU_CVT_F32_UBYTE0_:%[0-9]+]]:_(s32) = G_AMDGPU_CVT_F32_UBYTE0 [[AND]]
106+
; CHECK-NEXT: $vgpr0 = COPY [[AMDGPU_CVT_F32_UBYTE0_]](s32)
102107
%0:_(s32) = COPY $vgpr0
103108
%1:_(s32) = G_CONSTANT i32 128
104109
%2:_(s32) = G_AND %0, %1
@@ -114,11 +119,12 @@ body: |
114119
115120
; CHECK-LABEL: name: sitofp_too_many_bits_to_f32
116121
; CHECK: liveins: $vgpr0
117-
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
118-
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 256
119-
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
120-
; CHECK: [[SITOFP:%[0-9]+]]:_(s32) = G_SITOFP [[AND]](s32)
121-
; CHECK: $vgpr0 = COPY [[SITOFP]](s32)
122+
; CHECK-NEXT: {{ $}}
123+
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
124+
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 256
125+
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
126+
; CHECK-NEXT: [[SITOFP:%[0-9]+]]:_(s32) = G_SITOFP [[AND]](s32)
127+
; CHECK-NEXT: $vgpr0 = COPY [[SITOFP]](s32)
122128
%0:_(s32) = COPY $vgpr0
123129
%1:_(s32) = G_CONSTANT i32 256
124130
%2:_(s32) = G_AND %0, %1
@@ -135,13 +141,14 @@ body: |
135141
136142
; CHECK-LABEL: name: uitofp_char_to_f16
137143
; CHECK: liveins: $vgpr0
138-
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
139-
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
140-
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
141-
; CHECK: [[AMDGPU_CVT_F32_UBYTE0_:%[0-9]+]]:_(s32) = G_AMDGPU_CVT_F32_UBYTE0 [[AND]]
142-
; CHECK: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[AMDGPU_CVT_F32_UBYTE0_]](s32)
143-
; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FPTRUNC]](s16)
144-
; CHECK: $vgpr0 = COPY [[ANYEXT]](s32)
144+
; CHECK-NEXT: {{ $}}
145+
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
146+
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
147+
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
148+
; CHECK-NEXT: [[AMDGPU_CVT_F32_UBYTE0_:%[0-9]+]]:_(s32) = G_AMDGPU_CVT_F32_UBYTE0 [[AND]]
149+
; CHECK-NEXT: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[AMDGPU_CVT_F32_UBYTE0_]](s32)
150+
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FPTRUNC]](s16)
151+
; CHECK-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
145152
%0:_(s32) = COPY $vgpr0
146153
%1:_(s32) = G_CONSTANT i32 255
147154
%2:_(s32) = G_AND %0, %1
@@ -159,13 +166,14 @@ body: |
159166
160167
; CHECK-LABEL: name: sitofp_char_to_f16
161168
; CHECK: liveins: $vgpr0
162-
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
163-
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
164-
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
165-
; CHECK: [[AMDGPU_CVT_F32_UBYTE0_:%[0-9]+]]:_(s32) = G_AMDGPU_CVT_F32_UBYTE0 [[AND]]
166-
; CHECK: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[AMDGPU_CVT_F32_UBYTE0_]](s32)
167-
; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FPTRUNC]](s16)
168-
; CHECK: $vgpr0 = COPY [[ANYEXT]](s32)
169+
; CHECK-NEXT: {{ $}}
170+
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
171+
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
172+
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
173+
; CHECK-NEXT: [[AMDGPU_CVT_F32_UBYTE0_:%[0-9]+]]:_(s32) = G_AMDGPU_CVT_F32_UBYTE0 [[AND]]
174+
; CHECK-NEXT: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[AMDGPU_CVT_F32_UBYTE0_]](s32)
175+
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FPTRUNC]](s16)
176+
; CHECK-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
169177
%0:_(s32) = COPY $vgpr0
170178
%1:_(s32) = G_CONSTANT i32 255
171179
%2:_(s32) = G_AND %0, %1
@@ -183,12 +191,13 @@ body: |
183191
184192
; CHECK-LABEL: name: uitofp_s64_char_to_f32
185193
; CHECK: liveins: $vgpr0_vgpr1
186-
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
187-
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 255
188-
; CHECK: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]]
189-
; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[AND]](s64)
190-
; CHECK: [[AMDGPU_CVT_F32_UBYTE0_:%[0-9]+]]:_(s32) = G_AMDGPU_CVT_F32_UBYTE0 [[TRUNC]]
191-
; CHECK: $vgpr0 = COPY [[AMDGPU_CVT_F32_UBYTE0_]](s32)
194+
; CHECK-NEXT: {{ $}}
195+
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
196+
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 255
197+
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]]
198+
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[AND]](s64)
199+
; CHECK-NEXT: [[AMDGPU_CVT_F32_UBYTE0_:%[0-9]+]]:_(s32) = G_AMDGPU_CVT_F32_UBYTE0 [[TRUNC]]
200+
; CHECK-NEXT: $vgpr0 = COPY [[AMDGPU_CVT_F32_UBYTE0_]](s32)
192201
%0:_(s64) = COPY $vgpr0_vgpr1
193202
%1:_(s64) = G_CONSTANT i64 255
194203
%2:_(s64) = G_AND %0, %1
@@ -205,12 +214,13 @@ body: |
205214
206215
; CHECK-LABEL: name: sitofp_s64_char_to_f32
207216
; CHECK: liveins: $vgpr0_vgpr1
208-
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
209-
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 255
210-
; CHECK: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]]
211-
; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[AND]](s64)
212-
; CHECK: [[AMDGPU_CVT_F32_UBYTE0_:%[0-9]+]]:_(s32) = G_AMDGPU_CVT_F32_UBYTE0 [[TRUNC]]
213-
; CHECK: $vgpr0 = COPY [[AMDGPU_CVT_F32_UBYTE0_]](s32)
217+
; CHECK-NEXT: {{ $}}
218+
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
219+
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 255
220+
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]]
221+
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[AND]](s64)
222+
; CHECK-NEXT: [[AMDGPU_CVT_F32_UBYTE0_:%[0-9]+]]:_(s32) = G_AMDGPU_CVT_F32_UBYTE0 [[TRUNC]]
223+
; CHECK-NEXT: $vgpr0 = COPY [[AMDGPU_CVT_F32_UBYTE0_]](s32)
214224
%0:_(s64) = COPY $vgpr0_vgpr1
215225
%1:_(s64) = G_CONSTANT i64 255
216226
%2:_(s64) = G_AND %0, %1
@@ -227,13 +237,14 @@ body: |
227237
228238
; CHECK-LABEL: name: uitofp_s16_char_to_f32
229239
; CHECK: liveins: $vgpr0
230-
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
231-
; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
232-
; CHECK: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
233-
; CHECK: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C]]
234-
; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[AND]](s16)
235-
; CHECK: [[AMDGPU_CVT_F32_UBYTE0_:%[0-9]+]]:_(s32) = G_AMDGPU_CVT_F32_UBYTE0 [[ANYEXT]]
236-
; CHECK: $vgpr0 = COPY [[AMDGPU_CVT_F32_UBYTE0_]](s32)
240+
; CHECK-NEXT: {{ $}}
241+
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
242+
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
243+
; CHECK-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
244+
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C]]
245+
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[AND]](s16)
246+
; CHECK-NEXT: [[AMDGPU_CVT_F32_UBYTE0_:%[0-9]+]]:_(s32) = G_AMDGPU_CVT_F32_UBYTE0 [[ANYEXT]]
247+
; CHECK-NEXT: $vgpr0 = COPY [[AMDGPU_CVT_F32_UBYTE0_]](s32)
237248
%0:_(s32) = COPY $vgpr0
238249
%1:_(s16) = G_TRUNC %0
239250
%2:_(s16) = G_CONSTANT i16 255
@@ -251,13 +262,14 @@ body: |
251262
252263
; CHECK-LABEL: name: sitofp_s16_char_to_f32
253264
; CHECK: liveins: $vgpr0
254-
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
255-
; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
256-
; CHECK: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
257-
; CHECK: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C]]
258-
; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[AND]](s16)
259-
; CHECK: [[AMDGPU_CVT_F32_UBYTE0_:%[0-9]+]]:_(s32) = G_AMDGPU_CVT_F32_UBYTE0 [[ANYEXT]]
260-
; CHECK: $vgpr0 = COPY [[AMDGPU_CVT_F32_UBYTE0_]](s32)
265+
; CHECK-NEXT: {{ $}}
266+
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
267+
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
268+
; CHECK-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
269+
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C]]
270+
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[AND]](s16)
271+
; CHECK-NEXT: [[AMDGPU_CVT_F32_UBYTE0_:%[0-9]+]]:_(s32) = G_AMDGPU_CVT_F32_UBYTE0 [[ANYEXT]]
272+
; CHECK-NEXT: $vgpr0 = COPY [[AMDGPU_CVT_F32_UBYTE0_]](s32)
261273
%0:_(s32) = COPY $vgpr0
262274
%1:_(s16) = G_TRUNC %0
263275
%2:_(s16) = G_CONSTANT i16 255

‎llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizercombiner-load-and-mask.mir

Lines changed: 6 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -11,11 +11,12 @@ body: |
1111
liveins: $vgpr0_vgpr1
1212
; CHECK-LABEL: name: zextload_from_load_and_mask
1313
; CHECK: liveins: $vgpr0_vgpr1
14-
; CHECK: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
15-
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 255
16-
; CHECK: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[COPY]](p1) :: (load (s64), addrspace 1)
17-
; CHECK: [[AND:%[0-9]+]]:_(s64) = G_AND [[LOAD]], [[C]]
18-
; CHECK: $vgpr0_vgpr1 = COPY [[AND]](s64)
14+
; CHECK-NEXT: {{ $}}
15+
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
16+
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 255
17+
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[COPY]](p1) :: (load (s64), addrspace 1)
18+
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[LOAD]], [[C]]
19+
; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[AND]](s64)
1920
%0:_(p1) = COPY $vgpr0_vgpr1
2021
%1:_(s64) = G_CONSTANT i64 255
2122
%2:_(s64) = G_LOAD %0 :: (load (s64), align 8, addrspace 1)

0 commit comments

Comments
 (0)