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[AArch64] Add aarch64_neon_vcmla{_rot{90,180,270}} intrinsics.
Add builtins required to implement vcmla and rotated variants from the ACLE Reviewed By: t.p.northover Differential Revision: https://reviews.llvm.org/D92929
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‎llvm/include/llvm/IR/IntrinsicsAArch64.td

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@@ -497,6 +497,11 @@ let TargetPrefix = "aarch64", IntrProperties = [IntrNoMem] in {
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// v8.3-A Floating-point complex add
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def int_aarch64_neon_vcadd_rot90 : AdvSIMD_2VectorArg_Intrinsic;
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def int_aarch64_neon_vcadd_rot270 : AdvSIMD_2VectorArg_Intrinsic;
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def int_aarch64_neon_vcmla_rot0 : AdvSIMD_3VectorArg_Intrinsic;
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def int_aarch64_neon_vcmla_rot90 : AdvSIMD_3VectorArg_Intrinsic;
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def int_aarch64_neon_vcmla_rot180 : AdvSIMD_3VectorArg_Intrinsic;
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def int_aarch64_neon_vcmla_rot270 : AdvSIMD_3VectorArg_Intrinsic;
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}
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let TargetPrefix = "aarch64" in { // All intrinsics start with "llvm.aarch64.".

‎llvm/lib/Target/AArch64/AArch64InstrInfo.td

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@@ -934,6 +934,27 @@ let Predicates = [HasComplxNum, HasNEON] in {
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}
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}
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multiclass FCMLA_PATS<ValueType ty, RegisterClass Reg> {
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def : Pat<(ty (int_aarch64_neon_vcmla_rot0 (ty Reg:$Rd), (ty Reg:$Rn), (ty Reg:$Rm))),
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(!cast<Instruction>("FCMLA" # ty) $Rd, $Rn, $Rm, 0)>;
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def : Pat<(ty (int_aarch64_neon_vcmla_rot90 (ty Reg:$Rd), (ty Reg:$Rn), (ty Reg:$Rm))),
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(!cast<Instruction>("FCMLA" # ty) $Rd, $Rn, $Rm, 1)>;
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def : Pat<(ty (int_aarch64_neon_vcmla_rot180 (ty Reg:$Rd), (ty Reg:$Rn), (ty Reg:$Rm))),
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(!cast<Instruction>("FCMLA" # ty) $Rd, $Rn, $Rm, 2)>;
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def : Pat<(ty (int_aarch64_neon_vcmla_rot270 (ty Reg:$Rd), (ty Reg:$Rn), (ty Reg:$Rm))),
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(!cast<Instruction>("FCMLA" # ty) $Rd, $Rn, $Rm, 3)>;
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}
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let Predicates = [HasComplxNum, HasNEON, HasFullFP16] in {
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defm : FCMLA_PATS<v4f16, V64>;
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defm : FCMLA_PATS<v8f16, V128>;
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}
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let Predicates = [HasComplxNum, HasNEON] in {
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defm : FCMLA_PATS<v2f32, V64>;
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defm : FCMLA_PATS<v4f32, V128>;
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defm : FCMLA_PATS<v2f64, V128>;
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}
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// v8.3a Pointer Authentication
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// These instructions inhabit part of the hint space and so can be used for
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// armv8 targets. Keeping the old HINT mnemonic when compiling without PA is

‎llvm/test/CodeGen/AArch64/neon-vcmla.ll

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; RUN: llc %s -mtriple=aarch64 -mattr=+v8.3a,+fullfp16 -o - | FileCheck %s
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define <4 x half> @test_16x4(<4 x half> %a, <4 x half> %b, <4 x half> %c) {
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entry:
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; CHECK-LABEL: test_16x4
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; CHECK: fcmla v{{[0-9]+}}.4h, v{{[0-9]+}}.4h, v{{[0-9]+}}.4h, #0
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;
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%res = tail call <4 x half> @llvm.aarch64.neon.vcmla.rot0.v4f16(<4 x half> %a, <4 x half> %b, <4 x half> %c)
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ret <4 x half> %res
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}
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define <4 x half> @test_rot90_16x4(<4 x half> %a, <4 x half> %b, <4 x half> %c) {
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entry:
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; CHECK-LABEL: test_rot90_16x4
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; CHECK: fcmla v{{[0-9]+}}.4h, v{{[0-9]+}}.4h, v{{[0-9]+}}.4h, #90
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;
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%res = tail call <4 x half> @llvm.aarch64.neon.vcmla.rot90.v4f16(<4 x half> %a, <4 x half> %b, <4 x half> %c)
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ret <4 x half> %res
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}
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define <4 x half> @test_rot180_16x4(<4 x half> %a, <4 x half> %b, <4 x half> %c) {
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entry:
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; CHECK-LABEL: test_rot180_16x4
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; CHECK: fcmla v{{[0-9]+}}.4h, v{{[0-9]+}}.4h, v{{[0-9]+}}.4h, #180
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;
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%res = tail call <4 x half> @llvm.aarch64.neon.vcmla.rot180.v4f16(<4 x half> %a, <4 x half> %b, <4 x half> %c)
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ret <4 x half> %res
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}
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define <4 x half> @test_rot270_16x4(<4 x half> %a, <4 x half> %b, <4 x half> %c) {
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entry:
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; CHECK-LABEL: test_rot270_16x4
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; CHECK: fcmla v{{[0-9]+}}.4h, v{{[0-9]+}}.4h, v{{[0-9]+}}.4h, #270
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;
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%res = tail call <4 x half> @llvm.aarch64.neon.vcmla.rot270.v4f16(<4 x half> %a, <4 x half> %b, <4 x half> %c)
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ret <4 x half> %res
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}
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define <2 x float> @test_32x2(<2 x float> %a, <2 x float> %b, <2 x float> %c) {
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entry:
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; CHECK-LABEL: test_32x2
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; CHECK: fcmla v{{[0-9]+}}.2s, v{{[0-9]+}}.2s, v{{[0-9]+}}.2s, #0
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;
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%res = tail call <2 x float> @llvm.aarch64.neon.vcmla.rot0.v2f32(<2 x float> %a, <2 x float> %b, <2 x float> %c)
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ret <2 x float> %res
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}
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define <2 x float> @test_rot90_32x2(<2 x float> %a, <2 x float> %b, <2 x float> %c) {
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entry:
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; CHECK-LABEL: test_rot90_32x2
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; CHECK: fcmla v{{[0-9]+}}.2s, v{{[0-9]+}}.2s, v{{[0-9]+}}.2s, #90
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;
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%res = tail call <2 x float> @llvm.aarch64.neon.vcmla.rot90.v2f32(<2 x float> %a, <2 x float> %b, <2 x float> %c)
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ret <2 x float> %res
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}
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define <2 x float> @test_rot180_32x2(<2 x float> %a, <2 x float> %b, <2 x float> %c) {
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entry:
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; CHECK-LABEL: test_rot180_32x2
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; CHECK: fcmla v{{[0-9]+}}.2s, v{{[0-9]+}}.2s, v{{[0-9]+}}.2s, #180
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;
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%res = tail call <2 x float> @llvm.aarch64.neon.vcmla.rot180.v2f32(<2 x float> %a, <2 x float> %b, <2 x float> %c)
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ret <2 x float> %res
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}
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define <2 x float> @test_rot270_32x2(<2 x float> %a, <2 x float> %b, <2 x float> %c) {
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entry:
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; CHECK-LABEL: test_rot270_32x2
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; CHECK: fcmla v{{[0-9]+}}.2s, v{{[0-9]+}}.2s, v{{[0-9]+}}.2s, #270
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;
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%res = tail call <2 x float> @llvm.aarch64.neon.vcmla.rot270.v2f32(<2 x float> %a, <2 x float> %b, <2 x float> %c)
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ret <2 x float> %res
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}
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define <8 x half> @test_16x8(<8 x half> %a, <8 x half> %b, <8 x half> %c) {
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entry:
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; CHECK-LABEL: test_16x8
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; CHECK: fcmla v{{[0-9]+}}.8h, v{{[0-9]+}}.8h, v{{[0-9]+}}.8h, #0
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;
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%res = tail call <8 x half> @llvm.aarch64.neon.vcmla.rot0.v8f16(<8 x half> %a, <8 x half> %b, <8 x half> %c)
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ret <8 x half> %res
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}
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define <8 x half> @test_rot90_16x8(<8 x half> %a, <8 x half> %b, <8 x half> %c) {
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entry:
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; CHECK-LABEL: test_rot90_16x8
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; CHECK: fcmla v{{[0-9]+}}.8h, v{{[0-9]+}}.8h, v{{[0-9]+}}.8h, #90
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;
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%res = tail call <8 x half> @llvm.aarch64.neon.vcmla.rot90.v8f16(<8 x half> %a, <8 x half> %b, <8 x half> %c)
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ret <8 x half> %res
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}
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define <8 x half> @test_rot180_16x8(<8 x half> %a, <8 x half> %b, <8 x half> %c) {
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entry:
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; CHECK-LABEL: test_rot180_16x8
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; CHECK: fcmla v{{[0-9]+}}.8h, v{{[0-9]+}}.8h, v{{[0-9]+}}.8h, #180
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;
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%res = tail call <8 x half> @llvm.aarch64.neon.vcmla.rot180.v8f16(<8 x half> %a, <8 x half> %b, <8 x half> %c)
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ret <8 x half> %res
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}
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define <8 x half> @test_rot270_16x8(<8 x half> %a, <8 x half> %b, <8 x half> %c) {
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entry:
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; CHECK-LABEL: test_rot270_16x8
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; CHECK: fcmla v{{[0-9]+}}.8h, v{{[0-9]+}}.8h, v{{[0-9]+}}.8h, #270
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;
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%res = tail call <8 x half> @llvm.aarch64.neon.vcmla.rot270.v8f16(<8 x half> %a, <8 x half> %b, <8 x half> %c)
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ret <8 x half> %res
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}
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define <4 x float> @test_32x4(<4 x float> %a, <4 x float> %b, <4 x float> %c) {
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entry:
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; CHECK-LABEL: test_32x4
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; CHECK: fcmla v{{[0-9]+}}.4s, v{{[0-9]+}}.4s, v{{[0-9]+}}.4s, #0
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;
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%res = tail call <4 x float> @llvm.aarch64.neon.vcmla.rot0.v4f32(<4 x float> %a, <4 x float> %b, <4 x float> %c)
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ret <4 x float> %res
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}
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define <4 x float> @test_rot90_32x4(<4 x float> %a, <4 x float> %b, <4 x float> %c) {
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entry:
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; CHECK-LABEL: test_rot90_32x4
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; CHECK: fcmla v{{[0-9]+}}.4s, v{{[0-9]+}}.4s, v{{[0-9]+}}.4s, #90
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;
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%res = tail call <4 x float> @llvm.aarch64.neon.vcmla.rot90.v4f32(<4 x float> %a, <4 x float> %b, <4 x float> %c)
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ret <4 x float> %res
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}
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define <4 x float> @test_rot180_32x4(<4 x float> %a, <4 x float> %b, <4 x float> %c) {
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entry:
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; CHECK-LABEL: test_rot180_32x4
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; CHECK: fcmla v{{[0-9]+}}.4s, v{{[0-9]+}}.4s, v{{[0-9]+}}.4s, #180
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;
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%res = tail call <4 x float> @llvm.aarch64.neon.vcmla.rot180.v4f32(<4 x float> %a, <4 x float> %b, <4 x float> %c)
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ret <4 x float> %res
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}
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define <4 x float> @test_rot270_32x4(<4 x float> %a, <4 x float> %b, <4 x float> %c) {
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entry:
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; CHECK-LABEL: test_rot270_32x4
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; CHECK: fcmla v{{[0-9]+}}.4s, v{{[0-9]+}}.4s, v{{[0-9]+}}.4s, #270
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;
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%res = tail call <4 x float> @llvm.aarch64.neon.vcmla.rot270.v4f32(<4 x float> %a, <4 x float> %b, <4 x float> %c)
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ret <4 x float> %res
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}
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define <2 x double> @test_64x2(<2 x double> %a, <2 x double> %b, <2 x double> %c) {
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entry:
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; CHECK-LABEL: test_64x2
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; CHECK: fcmla v{{[0-9]+}}.2d, v{{[0-9]+}}.2d, v{{[0-9]+}}.2d, #0
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;
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%res = tail call <2 x double> @llvm.aarch64.neon.vcmla.rot0.v2f64(<2 x double> %a, <2 x double> %b, <2 x double> %c)
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ret <2 x double> %res
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}
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define <2 x double> @test_rot90_64x2(<2 x double> %a, <2 x double> %b, <2 x double> %c) {
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entry:
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; CHECK-LABEL: test_rot90_64x2
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; CHECK: fcmla v{{[0-9]+}}.2d, v{{[0-9]+}}.2d, v{{[0-9]+}}.2d, #90
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;
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%res = tail call <2 x double> @llvm.aarch64.neon.vcmla.rot90.v2f64(<2 x double> %a, <2 x double> %b, <2 x double> %c)
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ret <2 x double> %res
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}
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define <2 x double> @test_rot180_64x2(<2 x double> %a, <2 x double> %b, <2 x double> %c) {
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entry:
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; CHECK-LABEL: test_rot180_64x2
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; CHECK: fcmla v{{[0-9]+}}.2d, v{{[0-9]+}}.2d, v{{[0-9]+}}.2d, #180
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;
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%res = tail call <2 x double> @llvm.aarch64.neon.vcmla.rot180.v2f64(<2 x double> %a, <2 x double> %b, <2 x double> %c)
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ret <2 x double> %res
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}
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define <2 x double> @test_rot270_64x2(<2 x double> %a, <2 x double> %b, <2 x double> %c) {
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entry:
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; CHECK-LABEL: test_rot270_64x2
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; CHECK: fcmla v{{[0-9]+}}.2d, v{{[0-9]+}}.2d, v{{[0-9]+}}.2d, #270
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;
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%res = tail call <2 x double> @llvm.aarch64.neon.vcmla.rot270.v2f64(<2 x double> %a, <2 x double> %b, <2 x double> %c)
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ret <2 x double> %res
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}
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declare <4 x half> @llvm.aarch64.neon.vcmla.rot0.v4f16(<4 x half>, <4 x half>, <4 x half>)
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declare <4 x half> @llvm.aarch64.neon.vcmla.rot90.v4f16(<4 x half>, <4 x half>, <4 x half>)
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declare <4 x half> @llvm.aarch64.neon.vcmla.rot180.v4f16(<4 x half>, <4 x half>, <4 x half>)
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declare <4 x half> @llvm.aarch64.neon.vcmla.rot270.v4f16(<4 x half>, <4 x half>, <4 x half>)
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declare <8 x half> @llvm.aarch64.neon.vcmla.rot0.v8f16(<8 x half>, <8 x half>, <8 x half>)
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declare <8 x half> @llvm.aarch64.neon.vcmla.rot90.v8f16(<8 x half>, <8 x half>, <8 x half>)
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declare <8 x half> @llvm.aarch64.neon.vcmla.rot180.v8f16(<8 x half>, <8 x half>, <8 x half>)
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declare <8 x half> @llvm.aarch64.neon.vcmla.rot270.v8f16(<8 x half>, <8 x half>, <8 x half>)
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declare <2 x float> @llvm.aarch64.neon.vcmla.rot0.v2f32(<2 x float>, <2 x float>, <2 x float>)
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declare <2 x float> @llvm.aarch64.neon.vcmla.rot90.v2f32(<2 x float>, <2 x float>, <2 x float>)
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declare <2 x float> @llvm.aarch64.neon.vcmla.rot180.v2f32(<2 x float>, <2 x float>, <2 x float>)
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declare <2 x float> @llvm.aarch64.neon.vcmla.rot270.v2f32(<2 x float>, <2 x float>, <2 x float>)
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declare <4 x float> @llvm.aarch64.neon.vcmla.rot0.v4f32(<4 x float>, <4 x float>, <4 x float>)
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declare <4 x float> @llvm.aarch64.neon.vcmla.rot90.v4f32(<4 x float>, <4 x float>, <4 x float>)
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declare <4 x float> @llvm.aarch64.neon.vcmla.rot180.v4f32(<4 x float>, <4 x float>, <4 x float>)
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declare <4 x float> @llvm.aarch64.neon.vcmla.rot270.v4f32(<4 x float>, <4 x float>, <4 x float>)
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declare <2 x double> @llvm.aarch64.neon.vcmla.rot0.v2f64(<2 x double>, <2 x double>, <2 x double>)
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declare <2 x double> @llvm.aarch64.neon.vcmla.rot90.v2f64(<2 x double>, <2 x double>, <2 x double>)
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declare <2 x double> @llvm.aarch64.neon.vcmla.rot180.v2f64(<2 x double>, <2 x double>, <2 x double>)
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declare <2 x double> @llvm.aarch64.neon.vcmla.rot270.v2f64(<2 x double>, <2 x double>, <2 x double>)

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