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[CI] Disable E2E tests failing on PVC (#14720)
This PR disable tests failing on PVC. GH issue to track disabled tests: #14826
1 parent 243f237 commit 4cdce55

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sycl/test-e2e/Basic/accessor/accessor.cpp

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// RUN: %{build} -DSYCL2020_DISABLE_DEPRECATION_WARNINGS -o %t.out
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// RUN: %{run} %t.out
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// https://github.com/intel/llvm/issues/14826
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// XFAIL: arch-intel_gpu_pvc
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//==----------------accessor.cpp - SYCL accessor basic test ----------------==//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// RUN: %{build} -Daccessor_new_api_test %S/Inputs/host_task_accessor.cpp -o %t.out
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// RUN: %{run} %t.out
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// Disabled on PVC without igc-dev due to timeout.
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// https://github.com/intel/llvm/issues/14826
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// UNSUPPORTED: arch-intel_gpu_pvc && !igc-dev

sycl/test-e2e/DeprecatedFeatures/set_arg_interop.cpp

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// REQUIRES: opencl, opencl_icd
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// https://github.com/intel/llvm/issues/14826
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// XFAIL: arch-intel_gpu_pvc
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// RUN: %{build} -D__SYCL_INTERNAL_API -o %t.out %opencl_lib -O3
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// RUN: %{run} %t.out
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sycl/test-e2e/DeviceArchitecture/device_architecture_comparison_on_device_aot.cpp

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// REQUIRES: arch-intel_gpu_pvc, ocloc
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// https://github.com/intel/llvm/issues/14826
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// XFAIL: arch-intel_gpu_pvc
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// RUN: %clangxx -fsycl -fsycl-targets=intel_gpu_pvc %s -o %t.out
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// RUN: %{run} %t.out
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sycl/test-e2e/DeviceCodeSplit/grf.cpp

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// compiler option
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// REQUIRES: arch-intel_gpu_pvc
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// https://github.com/intel/llvm/issues/14826
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// XFAIL: *
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// RUN: %{build} -o %t.out
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// Don't use SYCL_UR_TRACE as the output from the L0 adapter logging interferes
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// with the regular UR traces we are checking.

sycl/test-e2e/ESIMD/lit.local.cfg

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# The current DG2 postcommit job only runs L0 anyway,
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# so there's no difference in coverage.
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# We should investigate why OCL fails separately.
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if 'gpu-intel-dg2' in config.available_features:
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# Check if any device has arch-intel_gpu_pvc
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has_arch_gpu_intel_pvc = any('arch-intel_gpu_pvc' in T for T in config.sycl_dev_features.values())
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if 'gpu-intel-dg2' in config.available_features or has_arch_gpu_intel_pvc:
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config.required_features += ['level_zero']
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# TODO: Remove this once the warnings are resolved

sycl/test-e2e/ESIMD/mask_expand_load.cpp

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// RUN: %{build} -fsycl-device-code-split=per_kernel -o %t.out
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// RUN: %{run} %t.out
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// https://github.com/intel/llvm/issues/14826
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// XFAIL: arch-intel_gpu_pvc
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// This is a basic test to validate the expanded load API.
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#include "esimd_test_utils.hpp"

sycl/test-e2e/ESIMD/named_barriers/loop.cpp

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// REQUIRES: arch-intel_gpu_pvc
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// RUN: %{build} -o %t.out
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// RUN: %{run} %t.out
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//
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// Disabled on PVC without igc-dev due to flaky failures.
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// https://github.com/intel/llvm/issues/14826
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// UNSUPPORTED: arch-intel_gpu_pvc && !igc-dev
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// Test checks support of named barrier in a loop in ESIMD kernel.
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// SLM and surface size is 32 bytes, 16 bytes per iteration.
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// Each iteration has 1 barrier and 1 producer. Producer stores data to SLM,

sycl/test-e2e/ESIMD/named_barriers/loop_extended.cpp

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// RUN: %{build} -o %t.out
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// RUN: %{run} %t.out
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//
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// Disabled on PVC due to flaky failures.
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// https://github.com/intel/llvm/issues/14826
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// UNSUPPORTED: arch-intel_gpu_pvc
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// Test checks support of named barrier in a loop in ESIMD kernel.
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// First iteration has 1 barrier and 1 producer, second - 2 barriers and 2
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// producers. Producer stores data to SLM, then all threads read SLM and store

sycl/test-e2e/Graph/Explicit/interop-level-zero-launch-kernel.cpp

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// Extra run to check for immediate-command-list in Level Zero
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// RUN: %if level_zero %{env SYCL_PI_LEVEL_ZERO_USE_IMMEDIATE_COMMANDLISTS=1 %{l0_leak_check} %{run} %t.out %S/../Inputs/Kernels/saxpy.spv 2>&1 | FileCheck %s --implicit-check-not=LEAK %}
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// https://github.com/intel/llvm/issues/14826
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// XFAIL: arch-intel_gpu_pvc
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#define GRAPH_E2E_EXPLICIT
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#include "../Inputs/interop-level-zero-launch-kernel.cpp"

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