[SYCL][ESIMD] Fix compilation break while using multiple bit shift functions (#6441)

* Fix multiple issues causing compilation break while using multiple bit shift functions

Author: fineg74

sycl/include/sycl/ext/intel/esimd/detail/elem_type_traits.hpp

@@ -655,13 +655,26 @@ struct computation_type<
   using Ty1 = element_type_t<T1>;
   using Ty2 = element_type_t<T2>;
   using EltTy = typename computation_type<Ty1, Ty2>::type;
-  static constexpr int N1 = is_simd_like_type_v<T1> ? T1::length : 0;
-  static constexpr int N2 = is_simd_like_type_v<T2> ? T2::length : 0;
-  static_assert((N1 == N2) || ((N1 & N2) == 0), "size mismatch");
+
+  static constexpr int N1 = [] {
+    if constexpr (is_simd_like_type_v<T1>) {
+      return T1::length;
+    } else {
+      return 0;
+    }
+  }();
+  static constexpr int N2 = [] {
+    if constexpr (is_simd_like_type_v<T2>) {
+      return T2::length;
+    } else {
+      return 0;
+    }
+  }();
+  static_assert((N1 == N2) || (N1 == 0) || (N2 == 0), "size mismatch");
   static constexpr int N = N1 ? N1 : N2;
 
 public:
-  using type = simd<EltTy, N1>;
+  using type = simd<EltTy, N>;
 };
 
 template <class T1, class T2 = T1>

sycl/include/sycl/ext/intel/experimental/esimd/detail/math_intrin.hpp

@@ -149,7 +149,7 @@ __ESIMD_INTRIN __ESIMD_raw_vec_t(T0, SZ)
 
   for (i = 0; i < SZ; i++) {
     SIMDCF_ELEMENT_SKIP(i);
-    ret = src0.get(i) << src1.get(i);
+    ret = src0[i] << src1[i];
     retv[i] = ret;
   }
   return retv;
@@ -167,7 +167,7 @@ __ESIMD_INTRIN __ESIMD_raw_vec_t(T0, SZ)
 
   for (i = 0; i < SZ; i++) {
     SIMDCF_ELEMENT_SKIP(i);
-    ret = src0.get(i) << src1.get(i);
+    ret = src0[i] << src1[i];
     retv[i] = ret;
   }
   return retv;
@@ -185,7 +185,7 @@ __ESIMD_INTRIN __ESIMD_raw_vec_t(T0, SZ)
 
   for (i = 0; i < SZ; i++) {
     SIMDCF_ELEMENT_SKIP(i);
-    ret = src0.get(i) << src1.get(i);
+    ret = src0[i] << src1[i];
     retv[i] = ret;
   }
   return retv;
@@ -203,7 +203,7 @@ __ESIMD_INTRIN __ESIMD_raw_vec_t(T0, SZ)
 
   for (i = 0; i < SZ; i++) {
     SIMDCF_ELEMENT_SKIP(i);
-    ret = src0.get(i) << src1.get(i);
+    ret = src0[i] << src1[i];
     retv[i] = ret;
   }
   return retv;
@@ -221,7 +221,7 @@ __ESIMD_INTRIN __ESIMD_raw_vec_t(T0, SZ)
 
   for (i = 0; i < SZ; i++) {
     SIMDCF_ELEMENT_SKIP(i);
-    ret = src0.get(i) << src1.get(i);
+    ret = src0[i] << src1[i];
     retv[i] = __ESIMD_EMU_DNS::satur<T0>::template saturate<T1>(ret, 1);
   }
   return retv;
@@ -239,7 +239,7 @@ __ESIMD_INTRIN __ESIMD_raw_vec_t(T0, SZ)
 
   for (i = 0; i < SZ; i++) {
     SIMDCF_ELEMENT_SKIP(i);
-    ret = src0.get(i) << src1.get(i);
+    ret = src0[i] << src1[i];
     retv[i] = __ESIMD_EMU_DNS::satur<T0>::template saturate<T1>(ret, 1);
   }
   return retv;
@@ -257,7 +257,7 @@ __ESIMD_INTRIN __ESIMD_raw_vec_t(T0, SZ)
 
   for (i = 0; i < SZ; i++) {
     SIMDCF_ELEMENT_SKIP(i);
-    ret = src0.get(i) << src1.get(i);
+    ret = src0[i] << src1[i];
     retv[i] = __ESIMD_EMU_DNS::satur<T0>::template saturate<T1>(ret, 1);
   }
   return retv;
@@ -275,7 +275,7 @@ __ESIMD_INTRIN __ESIMD_raw_vec_t(T0, SZ)
 
   for (i = 0; i < SZ; i++) {
     SIMDCF_ELEMENT_SKIP(i);
-    ret = src0.get(i) << src1.get(i);
+    ret = src0[i] << src1[i];
     retv[i] = __ESIMD_EMU_DNS::satur<T0>::template saturate<T1>(ret, 1);
   }
   return retv;