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[StatepointLowering] Only export STATEPOINT results if used in nonlocal blocks.
Cuurently we always export STATEPOINT results (GC pointers lowered via VRegs) to virtual registers. When processing gc.relocate instructions we have to generate CopyFromRegs node and then export it to VReg again if gc.relocate is used in other basic blocks. This results in generation of extra COPY MIR instruction if statepoint and its gc.relocate are in the same BB, but gc.relocate result is used in other blocks. This patch changes this behavior to export statepoint results only if used in other basic blocks. For local uses StatepointLoweringState.(get|set)Location() API is used to communicate appropriate statepoint result from `LowerStatepoint()` to `visitGCRelocate()` This is NFC and is purely compile time optimization. On big methids it can improve codegen compile time up to 10%. Reviewed By: reames Differential Revision: https://reviews.llvm.org/D124444
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‎llvm/include/llvm/CodeGen/FunctionLoweringInfo.h

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -101,6 +101,10 @@ class FunctionLoweringInfo {
101101
// Value was lowered to tied def and gc.relocate should be replaced with
102102
// copy from vreg.
103103
VReg,
104+
// Value was lowered to tied def and gc.relocate should be replaced with
105+
// SDValue kept in StatepointLoweringInfo structure. This valid for local
106+
// relocates only.
107+
SDValueNode,
104108
} type = NoRelocate;
105109
// Payload contains either frame index of the stack slot in which the value
106110
// was spilled, or virtual register which contains the re-definition.

‎llvm/lib/CodeGen/SelectionDAG/StatepointLowering.cpp

Lines changed: 30 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -884,21 +884,33 @@ SDValue SelectionDAGBuilder::LowerAsSTATEPOINT(
884884
DAG.getMachineNode(TargetOpcode::STATEPOINT, getCurSDLoc(), NodeTys, Ops);
885885
DAG.setNodeMemRefs(StatepointMCNode, MemRefs);
886886

887-
// For values lowered to tied-defs, create the virtual registers. Note that
888-
// for simplicity, we *always* create a vreg even within a single block.
887+
// For values lowered to tied-defs, create the virtual registers if used
888+
// in other blocks. For local gc.relocate record appropriate statepoint
889+
// result in StatepointLoweringState.
889890
DenseMap<SDValue, Register> VirtRegs;
890891
for (const auto *Relocate : SI.GCRelocates) {
891892
Value *Derived = Relocate->getDerivedPtr();
892893
SDValue SD = getValue(Derived);
893894
if (!LowerAsVReg.count(SD))
894895
continue;
895896

897+
SDValue Relocated = SDValue(StatepointMCNode, LowerAsVReg[SD]);
898+
899+
// Handle local relocate. Note that different relocates might
900+
// map to the same SDValue.
901+
if (SI.StatepointInstr->getParent() == Relocate->getParent()) {
902+
SDValue Res = StatepointLowering.getLocation(SD);
903+
if (Res)
904+
assert(Res == Relocated);
905+
else
906+
StatepointLowering.setLocation(SD, Relocated);
907+
continue;
908+
}
909+
896910
// Handle multiple gc.relocates of the same input efficiently.
897911
if (VirtRegs.count(SD))
898912
continue;
899913

900-
SDValue Relocated = SDValue(StatepointMCNode, LowerAsVReg[SD]);
901-
902914
auto *RetTy = Relocate->getType();
903915
Register Reg = FuncInfo.CreateRegs(RetTy);
904916
RegsForValue RFV(*DAG.getContext(), DAG.getTargetLoweringInfo(),
@@ -919,8 +931,13 @@ SDValue SelectionDAGBuilder::LowerAsSTATEPOINT(
919931
SDValue SDV = getValue(V);
920932
SDValue Loc = StatepointLowering.getLocation(SDV);
921933

934+
bool IsLocal = (Relocate->getParent() == StatepointInstr->getParent());
935+
922936
RecordType Record;
923-
if (LowerAsVReg.count(SDV)) {
937+
if (IsLocal && LowerAsVReg.count(SDV)) {
938+
// Result is already stored in StatepointLowering
939+
Record.type = RecordType::SDValueNode;
940+
} else if (LowerAsVReg.count(SDV)) {
924941
Record.type = RecordType::VReg;
925942
assert(VirtRegs.count(SDV));
926943
Record.payload.Reg = VirtRegs[SDV];
@@ -1219,6 +1236,14 @@ void SelectionDAGBuilder::visitGCRelocate(const GCRelocateInst &Relocate) {
12191236
const RecordType &Record = SlotIt->second;
12201237

12211238
// If relocation was done via virtual register..
1239+
if (Record.type == RecordType::SDValueNode) {
1240+
assert(Relocate.getStatepoint()->getParent() == Relocate.getParent() &&
1241+
"Nonlocal gc.relocate mapped via SDValue");
1242+
SDValue SDV = StatepointLowering.getLocation(getValue(DerivedPtr));
1243+
assert(SDV.getNode() && "empty SDValue");
1244+
setValue(&Relocate, SDV);
1245+
return;
1246+
}
12221247
if (Record.type == RecordType::VReg) {
12231248
Register InReg = Record.payload.Reg;
12241249
RegsForValue RFV(*DAG.getContext(), DAG.getTargetLoweringInfo(),

‎llvm/test/CodeGen/X86/statepoint-vreg-details.ll

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -322,14 +322,14 @@ define i8 addrspace(1)* @test_isel_sched(i8 addrspace(1)* %0, i8 addrspace(1)* %
322322
;CHECK-VREG: %1:gr64 = COPY $rsi
323323
;CHECK-VREG: %0:gr64 = COPY $rdi
324324
;CHECK-VREG: TEST32rr %2, %2, implicit-def $eflags
325-
;CHECK-VREG: %5:gr64 = CMOV64rr %1, %0, 4, implicit $eflags
326-
;CHECK-VREG: %6:gr32 = MOV32r0 implicit-def dead $eflags
327-
;CHECK-VREG: %7:gr64 = SUBREG_TO_REG 0, killed %6, %subreg.sub_32bit
328-
;CHECK-VREG: $rdi = COPY %7
329-
;CHECK-VREG: $rsi = COPY %5
330-
;CHECK-VREG: %3:gr64, %4:gr64 = STATEPOINT 10, 0, 2, @bar, $rdi, $rsi, 2, 0, 2, 0, 2, 0, 2, 2, %1(tied-def 0), %0(tied-def 1), 2, 0, 2, 2, 0, 0, 1, 1, csr_64, implicit-def $rsp, implicit-def $ssp
325+
;CHECK-VREG: %3:gr64 = CMOV64rr %1, %0, 4, implicit $eflags
326+
;CHECK-VREG: %4:gr32 = MOV32r0 implicit-def dead $eflags
327+
;CHECK-VREG: %5:gr64 = SUBREG_TO_REG 0, killed %4, %subreg.sub_32bit
328+
;CHECK-VREG: $rdi = COPY %5
329+
;CHECK-VREG: $rsi = COPY %3
330+
;CHECK-VREG: %6:gr64, %7:gr64 = STATEPOINT 10, 0, 2, @bar, $rdi, $rsi, 2, 0, 2, 0, 2, 0, 2, 2, %1(tied-def 0), %0(tied-def 1), 2, 0, 2, 2, 0, 0, 1, 1, csr_64, implicit-def $rsp, implicit-def $ssp
331331
;CHECK-VREG: TEST32rr %2, %2, implicit-def $eflags
332-
;CHECK-VREG: %8:gr64 = CMOV64rr %3, %4, 4, implicit $eflags
332+
;CHECK-VREG: %8:gr64 = CMOV64rr %6, killed %7, 4, implicit $eflags
333333
;CHECK-VREG: $rax = COPY %8
334334
;CHECK-VREG: RET 0, $rax
335335
entry:
@@ -342,14 +342,14 @@ entry:
342342
ret i8 addrspace(1)* %res
343343
}
344344

345-
; Show that ISEL of gc.relocate used in other BB does generate extra COPY instruction.
345+
; Check that ISEL of gc.relocate used in other BB does not generate extra COPY instruction.
346346
define i1 @test_cross_bb_reloc(i32 addrspace(1)* %a, i1 %external_cond) gc "statepoint-example" {
347347
; CHECK-VREG_LABEL: test_cross_bb_reloc:
348348
; CHECK-VREG: bb.0.entry:
349349
; CHECK-VREG: [[VREG:%[^ ]+]]:gr64 = STATEPOINT 0, 0, 0, @return_i1, 2, 0, 2, 0, 2, 0, 2, 1, %2(tied-def 0), 2, 0, 2, 1, 0, 0, csr_64, implicit-def $rsp, implicit-def $ssp, implicit-def $al
350-
; CHECK-VREG: [[EXTRA:%[^ ]+]]:gr64 = COPY [[VREG]]
350+
; CHECK-VREG-NOT: COPY [[VREG]]
351351
; CHECK-VREG: bb.1.left:
352-
; CHECK-VREG: $rdi = COPY [[EXTRA]]
352+
; CHECK-VREG: $rdi = COPY [[VREG]]
353353
; CHECK-VREG: CALL64pcrel32 @consume, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit-def $rsp, implicit-def $ssp
354354
; CHECK-VREG: $al = COPY %1
355355
; CHECK-VREG: RET 0, $al

‎llvm/test/CodeGen/X86/statepoint-vreg-unlimited-tied-opnds.ll

Lines changed: 37 additions & 37 deletions
Original file line numberDiff line numberDiff line change
@@ -12,43 +12,43 @@ define i32 @test_spill(
1212
i32 addrspace(1)* %arg12, i32 addrspace(1)* %arg13, i32 addrspace(1)* %arg14, i32 addrspace(1)* %arg15, i32 addrspace(1)* %arg16, i32 addrspace(1)* %arg17
1313
) gc "statepoint-example" {
1414
; CHECK-VREG-LABEL: test_spill
15-
; CHECK-VREG: %18:gr64 = COPY $r9
16-
; CHECK-VREG: %19:gr64 = COPY $r8
17-
; CHECK-VREG: %20:gr64 = COPY $rcx
18-
; CHECK-VREG: %21:gr64 = COPY $rdx
19-
; CHECK-VREG: %22:gr64 = COPY $rsi
20-
; CHECK-VREG: %23:gr64 = COPY $rdi
21-
; CHECK-VREG: %17:gr64 = MOV64rm %fixed-stack.11, 1, $noreg, 0, $noreg :: (load (s64) from %fixed-stack.11, align 16)
22-
; CHECK-VREG: %16:gr64 = MOV64rm %fixed-stack.10, 1, $noreg, 0, $noreg :: (load (s64) from %fixed-stack.10)
23-
; CHECK-VREG: %15:gr64 = MOV64rm %fixed-stack.9, 1, $noreg, 0, $noreg :: (load (s64) from %fixed-stack.9, align 16)
24-
; CHECK-VREG: %14:gr64 = MOV64rm %fixed-stack.8, 1, $noreg, 0, $noreg :: (load (s64) from %fixed-stack.8)
25-
; CHECK-VREG: %13:gr64 = MOV64rm %fixed-stack.7, 1, $noreg, 0, $noreg :: (load (s64) from %fixed-stack.7, align 16)
26-
; CHECK-VREG: %12:gr64 = MOV64rm %fixed-stack.6, 1, $noreg, 0, $noreg :: (load (s64) from %fixed-stack.6)
27-
; CHECK-VREG: %11:gr64 = MOV64rm %fixed-stack.5, 1, $noreg, 0, $noreg :: (load (s64) from %fixed-stack.5, align 16)
28-
; CHECK-VREG: %10:gr64 = MOV64rm %fixed-stack.4, 1, $noreg, 0, $noreg :: (load (s64) from %fixed-stack.4)
29-
; CHECK-VREG: %9:gr64 = MOV64rm %fixed-stack.3, 1, $noreg, 0, $noreg :: (load (s64) from %fixed-stack.3, align 16)
30-
; CHECK-VREG: %8:gr64 = MOV64rm %fixed-stack.2, 1, $noreg, 0, $noreg :: (load (s64) from %fixed-stack.2)
31-
; CHECK-VREG: %7:gr64 = MOV64rm %fixed-stack.1, 1, $noreg, 0, $noreg :: (load (s64) from %fixed-stack.1, align 16)
32-
; CHECK-VREG: %6:gr64 = MOV64rm %fixed-stack.0, 1, $noreg, 0, $noreg :: (load (s64) from %fixed-stack.0)
33-
; CHECK-VREG: %6:gr64, %7:gr64, %8:gr64, %9:gr64, %10:gr64, %11:gr64, %12:gr64, %13:gr64, %14:gr64, %15:gr64, %16:gr64, %17:gr64, %18:gr64, %19:gr64, %20:gr64, %21:gr64, %22:gr64, %23:gr64 = STATEPOINT 0, 0, 0, @func, 2, 0, 2, 0, 2, 0, 2, 18, %6(tied-def 0), %7(tied-def 1), %8(tied-def 2), %9(tied-def 3), %10(tied-def 4), %11(tied-def 5), %12(tied-def 6), %13(tied-def 7), %14(tied-def 8), %15(tied-def 9), %16(tied-def 10), %17(tied-def 11), %18(tied-def 12), %19(tied-def 13), %20(tied-def 14), %21(tied-def 15), %22(tied-def 16), %23(tied-def 17), 2, 0, 2, 18, 0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15, 16, 16, 17, 17, csr_64, implicit-def $rsp, implicit-def $ssp
34-
; CHECK-VREG: %38:gr32 = MOV32rm %23, 1, $noreg, 4, $noreg :: (load (s32) from %ir.gep00, addrspace 1)
35-
; CHECK-VREG: %38:gr32 = ADD32rm %38, %22, 1, $noreg, 8, $noreg, implicit-def dead $eflags :: (load (s32) from %ir.gep01, addrspace 1)
36-
; CHECK-VREG: %38:gr32 = ADD32rm %38, %21, 1, $noreg, 12, $noreg, implicit-def dead $eflags :: (load (s32) from %ir.gep02, addrspace 1)
37-
; CHECK-VREG: %38:gr32 = ADD32rm %38, %20, 1, $noreg, 16, $noreg, implicit-def dead $eflags :: (load (s32) from %ir.gep03, addrspace 1)
38-
; CHECK-VREG: %38:gr32 = ADD32rm %38, %19, 1, $noreg, 20, $noreg, implicit-def dead $eflags :: (load (s32) from %ir.gep04, addrspace 1)
39-
; CHECK-VREG: %38:gr32 = ADD32rm %38, %18, 1, $noreg, 24, $noreg, implicit-def dead $eflags :: (load (s32) from %ir.gep05, addrspace 1)
40-
; CHECK-VREG: %38:gr32 = ADD32rm %38, %17, 1, $noreg, 28, $noreg, implicit-def dead $eflags :: (load (s32) from %ir.gep06, addrspace 1)
41-
; CHECK-VREG: %38:gr32 = ADD32rm %38, %16, 1, $noreg, 32, $noreg, implicit-def dead $eflags :: (load (s32) from %ir.gep07, addrspace 1)
42-
; CHECK-VREG: %38:gr32 = ADD32rm %38, %15, 1, $noreg, 36, $noreg, implicit-def dead $eflags :: (load (s32) from %ir.gep08, addrspace 1)
43-
; CHECK-VREG: %38:gr32 = ADD32rm %38, %14, 1, $noreg, 40, $noreg, implicit-def dead $eflags :: (load (s32) from %ir.gep09, addrspace 1)
44-
; CHECK-VREG: %38:gr32 = ADD32rm %38, %13, 1, $noreg, 44, $noreg, implicit-def dead $eflags :: (load (s32) from %ir.gep10, addrspace 1)
45-
; CHECK-VREG: %38:gr32 = ADD32rm %38, %12, 1, $noreg, 48, $noreg, implicit-def dead $eflags :: (load (s32) from %ir.gep11, addrspace 1)
46-
; CHECK-VREG: %38:gr32 = ADD32rm %38, %11, 1, $noreg, 52, $noreg, implicit-def dead $eflags :: (load (s32) from %ir.gep12, addrspace 1)
47-
; CHECK-VREG: %38:gr32 = ADD32rm %38, %10, 1, $noreg, 56, $noreg, implicit-def dead $eflags :: (load (s32) from %ir.gep13, addrspace 1)
48-
; CHECK-VREG: %38:gr32 = ADD32rm %38, %9, 1, $noreg, 60, $noreg, implicit-def dead $eflags :: (load (s32) from %ir.gep14, addrspace 1)
49-
; CHECK-VREG: %38:gr32 = ADD32rm %38, %8, 1, $noreg, 64, $noreg, implicit-def dead $eflags :: (load (s32) from %ir.gep15, addrspace 1)
50-
; CHECK-VREG: %38:gr32 = ADD32rm %38, %7, 1, $noreg, 68, $noreg, implicit-def dead $eflags :: (load (s32) from %ir.gep16, addrspace 1)
51-
; CHECK-VREG: %38:gr32 = ADD32rm %38, %6, 1, $noreg, 72, $noreg, implicit-def dead $eflags :: (load (s32) from %ir.gep17, addrspace 1)
15+
; CHECK-VREG: %30:gr64 = COPY $r9
16+
; CHECK-VREG: %31:gr64 = COPY $r8
17+
; CHECK-VREG: %32:gr64 = COPY $rcx
18+
; CHECK-VREG: %33:gr64 = COPY $rdx
19+
; CHECK-VREG: %34:gr64 = COPY $rsi
20+
; CHECK-VREG: %35:gr64 = COPY $rdi
21+
; CHECK-VREG: %29:gr64 = MOV64rm %fixed-stack.11, 1, $noreg, 0, $noreg :: (load (s64) from %fixed-stack.11, align 16)
22+
; CHECK-VREG: %28:gr64 = MOV64rm %fixed-stack.10, 1, $noreg, 0, $noreg :: (load (s64) from %fixed-stack.10)
23+
; CHECK-VREG: %27:gr64 = MOV64rm %fixed-stack.9, 1, $noreg, 0, $noreg :: (load (s64) from %fixed-stack.9, align 16)
24+
; CHECK-VREG: %26:gr64 = MOV64rm %fixed-stack.8, 1, $noreg, 0, $noreg :: (load (s64) from %fixed-stack.8)
25+
; CHECK-VREG: %25:gr64 = MOV64rm %fixed-stack.7, 1, $noreg, 0, $noreg :: (load (s64) from %fixed-stack.7, align 16)
26+
; CHECK-VREG: %24:gr64 = MOV64rm %fixed-stack.6, 1, $noreg, 0, $noreg :: (load (s64) from %fixed-stack.6)
27+
; CHECK-VREG: %23:gr64 = MOV64rm %fixed-stack.5, 1, $noreg, 0, $noreg :: (load (s64) from %fixed-stack.5, align 16)
28+
; CHECK-VREG: %22:gr64 = MOV64rm %fixed-stack.4, 1, $noreg, 0, $noreg :: (load (s64) from %fixed-stack.4)
29+
; CHECK-VREG: %21:gr64 = MOV64rm %fixed-stack.3, 1, $noreg, 0, $noreg :: (load (s64) from %fixed-stack.3, align 16)
30+
; CHECK-VREG: %20:gr64 = MOV64rm %fixed-stack.2, 1, $noreg, 0, $noreg :: (load (s64) from %fixed-stack.2)
31+
; CHECK-VREG: %19:gr64 = MOV64rm %fixed-stack.1, 1, $noreg, 0, $noreg :: (load (s64) from %fixed-stack.1, align 16)
32+
; CHECK-VREG: %18:gr64 = MOV64rm %fixed-stack.0, 1, $noreg, 0, $noreg :: (load (s64) from %fixed-stack.0)
33+
; CHECK-VREG: %18:gr64, %19:gr64, %20:gr64, %21:gr64, %22:gr64, %23:gr64, %24:gr64, %25:gr64, %26:gr64, %27:gr64, %28:gr64, %29:gr64, %30:gr64, %31:gr64, %32:gr64, %33:gr64, %34:gr64, %35:gr64 = STATEPOINT 0, 0, 0, @func, 2, 0, 2, 0, 2, 0, 2, 18, %18(tied-def 0), %19(tied-def 1), %20(tied-def 2), %21(tied-def 3), %22(tied-def 4), %23(tied-def 5), %24(tied-def 6), %25(tied-def 7), %26(tied-def 8), %27(tied-def 9), %28(tied-def 10), %29(tied-def 11), %30(tied-def 12), %31(tied-def 13), %32(tied-def 14), %33(tied-def 15), %34(tied-def 16), %35(tied-def 17), 2, 0, 2, 18, 0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15, 16, 16, 17, 17, csr_64, implicit-def $rsp, implicit-def $ssp
34+
; CHECK-VREG: %38:gr32 = MOV32rm %35, 1, $noreg, 4, $noreg :: (load (s32) from %ir.gep00, addrspace 1)
35+
; CHECK-VREG: %38:gr32 = ADD32rm %38, %34, 1, $noreg, 8, $noreg, implicit-def dead $eflags :: (load (s32) from %ir.gep01, addrspace 1)
36+
; CHECK-VREG: %38:gr32 = ADD32rm %38, %33, 1, $noreg, 12, $noreg, implicit-def dead $eflags :: (load (s32) from %ir.gep02, addrspace 1)
37+
; CHECK-VREG: %38:gr32 = ADD32rm %38, %32, 1, $noreg, 16, $noreg, implicit-def dead $eflags :: (load (s32) from %ir.gep03, addrspace 1)
38+
; CHECK-VREG: %38:gr32 = ADD32rm %38, %31, 1, $noreg, 20, $noreg, implicit-def dead $eflags :: (load (s32) from %ir.gep04, addrspace 1)
39+
; CHECK-VREG: %38:gr32 = ADD32rm %38, %30, 1, $noreg, 24, $noreg, implicit-def dead $eflags :: (load (s32) from %ir.gep05, addrspace 1)
40+
; CHECK-VREG: %38:gr32 = ADD32rm %38, %29, 1, $noreg, 28, $noreg, implicit-def dead $eflags :: (load (s32) from %ir.gep06, addrspace 1)
41+
; CHECK-VREG: %38:gr32 = ADD32rm %38, %28, 1, $noreg, 32, $noreg, implicit-def dead $eflags :: (load (s32) from %ir.gep07, addrspace 1)
42+
; CHECK-VREG: %38:gr32 = ADD32rm %38, %27, 1, $noreg, 36, $noreg, implicit-def dead $eflags :: (load (s32) from %ir.gep08, addrspace 1)
43+
; CHECK-VREG: %38:gr32 = ADD32rm %38, %26, 1, $noreg, 40, $noreg, implicit-def dead $eflags :: (load (s32) from %ir.gep09, addrspace 1)
44+
; CHECK-VREG: %38:gr32 = ADD32rm %38, %25, 1, $noreg, 44, $noreg, implicit-def dead $eflags :: (load (s32) from %ir.gep10, addrspace 1)
45+
; CHECK-VREG: %38:gr32 = ADD32rm %38, %24, 1, $noreg, 48, $noreg, implicit-def dead $eflags :: (load (s32) from %ir.gep11, addrspace 1)
46+
; CHECK-VREG: %38:gr32 = ADD32rm %38, %23, 1, $noreg, 52, $noreg, implicit-def dead $eflags :: (load (s32) from %ir.gep12, addrspace 1)
47+
; CHECK-VREG: %38:gr32 = ADD32rm %38, %22, 1, $noreg, 56, $noreg, implicit-def dead $eflags :: (load (s32) from %ir.gep13, addrspace 1)
48+
; CHECK-VREG: %38:gr32 = ADD32rm %38, %21, 1, $noreg, 60, $noreg, implicit-def dead $eflags :: (load (s32) from %ir.gep14, addrspace 1)
49+
; CHECK-VREG: %38:gr32 = ADD32rm %38, %20, 1, $noreg, 64, $noreg, implicit-def dead $eflags :: (load (s32) from %ir.gep15, addrspace 1)
50+
; CHECK-VREG: %38:gr32 = ADD32rm %38, %19, 1, $noreg, 68, $noreg, implicit-def dead $eflags :: (load (s32) from %ir.gep16, addrspace 1)
51+
; CHECK-VREG: %38:gr32 = ADD32rm %38, %18, 1, $noreg, 72, $noreg, implicit-def dead $eflags :: (load (s32) from %ir.gep17, addrspace 1)
5252
; CHECK-VREG: $eax = COPY %38
5353

5454
; CHECK-PREG: renamable $rbx = COPY $r9

‎llvm/test/CodeGen/X86/statepoint-vreg.ll

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -434,20 +434,20 @@ define void @test_sched(float %0, i32 %1, i8 addrspace(1)* %2) gc "statepoint-ex
434434
; CHECK-NEXT: movsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
435435
; CHECK-NEXT: nopl 8(%rax,%rax)
436436
; CHECK-NEXT: .Ltmp14:
437-
; CHECK-NEXT: movsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 8-byte Reload
438-
; CHECK-NEXT: # xmm0 = mem[0],zero
439-
; CHECK-NEXT: movsd %xmm0, {{[0-9]+}}(%rsp)
440437
; CHECK-NEXT: movss {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 4-byte Reload
441438
; CHECK-NEXT: # xmm0 = mem[0],zero,zero,zero
442-
; CHECK-NEXT: movss %xmm0, (%rsp)
443-
; CHECK-NEXT: nopl 8(%rax,%rax)
444-
; CHECK-NEXT: .Ltmp15:
439+
; CHECK-NEXT: movss %xmm0, {{[-0-9]*}}(%rsp)
445440
; CHECK-NEXT: movsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 8-byte Reload
446441
; CHECK-NEXT: # xmm0 = mem[0],zero
447442
; CHECK-NEXT: movsd %xmm0, {{[0-9]+}}(%rsp)
443+
; CHECK-NEXT: nopl 8(%rax,%rax)
444+
; CHECK-NEXT: .Ltmp15:
448445
; CHECK-NEXT: movss {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 4-byte Reload
449446
; CHECK-NEXT: # xmm0 = mem[0],zero,zero,zero
450447
; CHECK-NEXT: movss %xmm0, (%rsp)
448+
; CHECK-NEXT: movsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 8-byte Reload
449+
; CHECK-NEXT: # xmm1 = mem[0],zero
450+
; CHECK-NEXT: movsd %xmm1, {{[0-9]+}}(%rsp)
451451
; CHECK-NEXT: nopl 8(%rax,%rax)
452452
; CHECK-NEXT: .Ltmp16:
453453
; CHECK-NEXT: xorl %eax, %eax

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