[Upstream] Fix number of new issues comming from upstream

* Fix NVPTX backend build issue
* Fix few tests by adding -opaque-pointers explicitly. We are behind
upstream on opaque pointers enabling and opaque pointers currently OFF.
So explicit flag is required.

Author: Pavel V Chupin

clang/test/CodeGenCUDA/amdgpu-asan.cu

@@ -6,17 +6,17 @@
 // Check sanitizer runtime library functions survive
 // optimizations without being removed or parameters altered.
 
-// RUN: %clang_cc1 %s -emit-llvm -o - -triple=amdgcn-amd-amdhsa \
+// RUN: %clang_cc1 %s -opaque-pointers -emit-llvm -o - -triple=amdgcn-amd-amdhsa \
 // RUN:   -fcuda-is-device -target-cpu gfx906 -fsanitize=address \
 // RUN:   -mlink-bitcode-file %t.asanrtl.bc -x hip \
 // RUN:   | FileCheck -check-prefixes=ASAN %s
 
-// RUN: %clang_cc1 %s -emit-llvm -o - -triple=amdgcn-amd-amdhsa \
+// RUN: %clang_cc1 %s -opaque-pointers -emit-llvm -o - -triple=amdgcn-amd-amdhsa \
 // RUN:   -fcuda-is-device -target-cpu gfx906 -fsanitize=address \
 // RUN:   -O3 -mlink-bitcode-file %t.asanrtl.bc -x hip \
 // RUN:   | FileCheck -check-prefixes=ASAN %s
 
-// RUN: %clang_cc1 %s -emit-llvm -o - -triple=amdgcn-amd-amdhsa \
+// RUN: %clang_cc1 %s -opaque-pointers -emit-llvm -o - -triple=amdgcn-amd-amdhsa \
 // RUN:   -fcuda-is-device -target-cpu gfx906 -x hip \
 // RUN:   | FileCheck %s
 

clang/test/Driver/linker-wrapper-image.c

@@ -3,9 +3,9 @@
 // REQUIRES: amdgpu-registered-target
 
 // RUN: clang-offload-packager -o %t.out --image=file=%S/Inputs/dummy-elf.o,kind=openmp,triple=nvptx64-nvidia-cuda,arch=sm_70
-// RUN: %clang -cc1 %s -triple x86_64-unknown-linux-gnu -emit-obj -o %t.o \
+// RUN: %clang -cc1 %s -triple x86_64-unknown-linux-gnu -opaque-pointers -emit-obj -o %t.o \
 // RUN:   -fembed-offload-object=%t.out
-// RUN: clang-linker-wrapper --print-wrapped-module --dry-run --host-triple x86_64-unknown-linux-gnu \
+// RUN: clang-linker-wrapper --print-wrapped-module -opaque-pointers --dry-run --host-triple x86_64-unknown-linux-gnu \
 // RUN:   -linker-path /usr/bin/ld -- %t.o -o a.out 2>&1 | FileCheck %s --check-prefix=OPENMP
 
 // OPENMP: @__start_omp_offloading_entries = external hidden constant %__tgt_offload_entry
@@ -30,9 +30,9 @@
 // OPENMP-NEXT: }
 
 // RUN: clang-offload-packager -o %t.out --image=file=%S/Inputs/dummy-elf.o,kind=cuda,triple=nvptx64-nvidia-cuda,arch=sm_70
-// RUN: %clang -cc1 %s -triple x86_64-unknown-linux-gnu -emit-obj -o %t.o \
+// RUN: %clang -cc1 %s -triple x86_64-unknown-linux-gnu -opaque-pointers -emit-obj -o %t.o \
 // RUN:   -fembed-offload-object=%t.out
-// RUN: clang-linker-wrapper --print-wrapped-module --dry-run --host-triple x86_64-unknown-linux-gnu \
+// RUN: clang-linker-wrapper --print-wrapped-module -opaque-pointers --dry-run --host-triple x86_64-unknown-linux-gnu \
 // RUN:   -linker-path /usr/bin/ld -- %t.o -o a.out 2>&1 | FileCheck %s --check-prefix=CUDA
 
 // CUDA: @.fatbin_image = internal constant [0 x i8] zeroinitializer, section ".nv_fatbin"

llvm/lib/Target/NVPTX/NVPTXIntrinsics.td

@@ -1038,8 +1038,6 @@ def INT_NVVM_RCP_RP_F : F_MATH_1<"rcp.rp.f32 \t$dst, $src0;",
 
 def INT_NVVM_RCP_APPROX_F : F_MATH_1<"rcp.approx.f32 \t$dst, $src0;",
   Float32Regs, Float32Regs, int_nvvm_rcp_approx_f>;
-def INT_NVVM_RCP_APPROX_FTZ_F : F_MATH_1<"rcp.approx.ftz.f32 \t$dst, $src0;",
-  Float32Regs, Float32Regs, int_nvvm_rcp_approx_ftz_f>;
 
 def INT_NVVM_RCP_RN_D : F_MATH_1<"rcp.rn.f64 \t$dst, $src0;", Float64Regs,
   Float64Regs, int_nvvm_rcp_rn_d>;

llvm/test/CodeGen/AMDGPU/GlobalISel/prelegalizer-combiner-divrem.mir

@@ -1,5 +1,5 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -run-pass=amdgpu-prelegalizer-combiner -verify-machineinstrs -o - %s | FileCheck %s
+# RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -run-pass=amdgpu-prelegalizer-combiner -opaque-pointers=1 -verify-machineinstrs -o - %s | FileCheck %s
 
 ---
 name: test_sdiv_srem

llvm/test/CodeGen/AMDGPU/merge-flat-load-store.mir

@@ -1,5 +1,5 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -run-pass=si-load-store-opt -verify-machineinstrs -o - %s | FileCheck -check-prefix=GCN %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -run-pass=si-load-store-opt -opaque-pointers=1 -verify-machineinstrs -o - %s | FileCheck -check-prefix=GCN %s
 
 ---
 name:            merge_flat_load_dword_2

llvm/test/CodeGen/AMDGPU/merge-flat-with-global-load-store.mir

@@ -1,5 +1,5 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -run-pass=si-load-store-opt -verify-machineinstrs -o - %s | FileCheck -check-prefix=GCN %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -run-pass=si-load-store-opt -opaque-pointers=1 -verify-machineinstrs -o - %s | FileCheck -check-prefix=GCN %s
 
 ---
 name:            merge_flat_global_load_dword_2

llvm/test/CodeGen/AMDGPU/merge-global-load-store.mir

@@ -1,5 +1,5 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -run-pass=si-load-store-opt -verify-machineinstrs -o - %s | FileCheck -check-prefix=GCN %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -run-pass=si-load-store-opt -opaque-pointers=1 -verify-machineinstrs -o - %s | FileCheck -check-prefix=GCN %s
 
 ---
 name:            merge_global_load_dword_2