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Revert "[SDAG] Allow scalable vectors in ComputeNumSignBits" and follow up
This reverts commits 3fb08d1 and f8c63a7. There was a "timeout for a Halide Hexagon test" reported. Revert until investigation complete.
1 parent 1fe1299 commit 102f05b

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7 files changed

+75
-58
lines changed

7 files changed

+75
-58
lines changed

‎llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

Lines changed: 10 additions & 35 deletions
Original file line numberDiff line numberDiff line change
@@ -3962,10 +3962,11 @@ bool SelectionDAG::isKnownToBeAPowerOfTwo(SDValue Val) const {
39623962
unsigned SelectionDAG::ComputeNumSignBits(SDValue Op, unsigned Depth) const {
39633963
EVT VT = Op.getValueType();
39643964

3965-
// Since the number of lanes in a scalable vector is unknown at compile time,
3966-
// we track one bit which is implicitly broadcast to all lanes. This means
3967-
// that all lanes in a scalable vector are considered demanded.
3968-
APInt DemandedElts = VT.isFixedLengthVector()
3965+
// TODO: Assume we don't know anything for now.
3966+
if (VT.isScalableVector())
3967+
return 1;
3968+
3969+
APInt DemandedElts = VT.isVector()
39693970
? APInt::getAllOnes(VT.getVectorNumElements())
39703971
: APInt(1, 1);
39713972
return ComputeNumSignBits(Op, DemandedElts, Depth);
@@ -3988,7 +3989,7 @@ unsigned SelectionDAG::ComputeNumSignBits(SDValue Op, const APInt &DemandedElts,
39883989
if (Depth >= MaxRecursionDepth)
39893990
return 1; // Limit search depth.
39903991

3991-
if (!DemandedElts)
3992+
if (!DemandedElts || VT.isScalableVector())
39923993
return 1; // No demanded elts, better to assume we don't know anything.
39933994

39943995
unsigned Opcode = Op.getOpcode();
@@ -4003,16 +4004,7 @@ unsigned SelectionDAG::ComputeNumSignBits(SDValue Op, const APInt &DemandedElts,
40034004
case ISD::MERGE_VALUES:
40044005
return ComputeNumSignBits(Op.getOperand(Op.getResNo()), DemandedElts,
40054006
Depth + 1);
4006-
case ISD::SPLAT_VECTOR: {
4007-
// Check if the sign bits of source go down as far as the truncated value.
4008-
unsigned NumSrcBits = Op.getOperand(0).getValueSizeInBits();
4009-
unsigned NumSrcSignBits = ComputeNumSignBits(Op.getOperand(0), Depth + 1);
4010-
if (NumSrcSignBits > (NumSrcBits - VTBits))
4011-
return NumSrcSignBits - (NumSrcBits - VTBits);
4012-
break;
4013-
}
40144007
case ISD::BUILD_VECTOR:
4015-
assert(!VT.isScalableVector());
40164008
Tmp = VTBits;
40174009
for (unsigned i = 0, e = Op.getNumOperands(); (i < e) && (Tmp > 1); ++i) {
40184010
if (!DemandedElts[i])
@@ -4057,8 +4049,6 @@ unsigned SelectionDAG::ComputeNumSignBits(SDValue Op, const APInt &DemandedElts,
40574049
}
40584050

40594051
case ISD::BITCAST: {
4060-
if (VT.isScalableVector())
4061-
break;
40624052
SDValue N0 = Op.getOperand(0);
40634053
EVT SrcVT = N0.getValueType();
40644054
unsigned SrcBits = SrcVT.getScalarSizeInBits();
@@ -4116,8 +4106,6 @@ unsigned SelectionDAG::ComputeNumSignBits(SDValue Op, const APInt &DemandedElts,
41164106
Tmp2 = ComputeNumSignBits(Op.getOperand(0), DemandedElts, Depth+1);
41174107
return std::max(Tmp, Tmp2);
41184108
case ISD::SIGN_EXTEND_VECTOR_INREG: {
4119-
if (VT.isScalableVector())
4120-
break;
41214109
SDValue Src = Op.getOperand(0);
41224110
EVT SrcVT = Src.getValueType();
41234111
APInt DemandedSrcElts = DemandedElts.zext(SrcVT.getVectorNumElements());
@@ -4335,8 +4323,6 @@ unsigned SelectionDAG::ComputeNumSignBits(SDValue Op, const APInt &DemandedElts,
43354323
break;
43364324
}
43374325
case ISD::EXTRACT_ELEMENT: {
4338-
if (VT.isScalableVector())
4339-
break;
43404326
const int KnownSign = ComputeNumSignBits(Op.getOperand(0), Depth+1);
43414327
const int BitWidth = Op.getValueSizeInBits();
43424328
const int Items = Op.getOperand(0).getValueSizeInBits() / BitWidth;
@@ -4350,8 +4336,6 @@ unsigned SelectionDAG::ComputeNumSignBits(SDValue Op, const APInt &DemandedElts,
43504336
return std::clamp(KnownSign - rIndex * BitWidth, 0, BitWidth);
43514337
}
43524338
case ISD::INSERT_VECTOR_ELT: {
4353-
if (VT.isScalableVector())
4354-
break;
43554339
// If we know the element index, split the demand between the
43564340
// source vector and the inserted element, otherwise assume we need
43574341
// the original demanded vector elements and the value.
@@ -4382,7 +4366,6 @@ unsigned SelectionDAG::ComputeNumSignBits(SDValue Op, const APInt &DemandedElts,
43824366
return Tmp;
43834367
}
43844368
case ISD::EXTRACT_VECTOR_ELT: {
4385-
assert(!VT.isScalableVector());
43864369
SDValue InVec = Op.getOperand(0);
43874370
SDValue EltNo = Op.getOperand(1);
43884371
EVT VecVT = InVec.getValueType();
@@ -4421,8 +4404,6 @@ unsigned SelectionDAG::ComputeNumSignBits(SDValue Op, const APInt &DemandedElts,
44214404
return ComputeNumSignBits(Src, DemandedSrcElts, Depth + 1);
44224405
}
44234406
case ISD::CONCAT_VECTORS: {
4424-
if (VT.isScalableVector())
4425-
break;
44264407
// Determine the minimum number of sign bits across all demanded
44274408
// elts of the input vectors. Early out if the result is already 1.
44284409
Tmp = std::numeric_limits<unsigned>::max();
@@ -4441,8 +4422,6 @@ unsigned SelectionDAG::ComputeNumSignBits(SDValue Op, const APInt &DemandedElts,
44414422
return Tmp;
44424423
}
44434424
case ISD::INSERT_SUBVECTOR: {
4444-
if (VT.isScalableVector())
4445-
break;
44464425
// Demand any elements from the subvector and the remainder from the src its
44474426
// inserted into.
44484427
SDValue Src = Op.getOperand(0);
@@ -4513,7 +4492,7 @@ unsigned SelectionDAG::ComputeNumSignBits(SDValue Op, const APInt &DemandedElts,
45134492
// We only need to handle vectors - computeKnownBits should handle
45144493
// scalar cases.
45154494
Type *CstTy = Cst->getType();
4516-
if (CstTy->isVectorTy() && !VT.isScalableVector() &&
4495+
if (CstTy->isVectorTy() &&
45174496
(NumElts * VTBits) == CstTy->getPrimitiveSizeInBits() &&
45184497
VTBits == CstTy->getScalarSizeInBits()) {
45194498
Tmp = VTBits;
@@ -4548,14 +4527,10 @@ unsigned SelectionDAG::ComputeNumSignBits(SDValue Op, const APInt &DemandedElts,
45484527
Opcode == ISD::INTRINSIC_WO_CHAIN ||
45494528
Opcode == ISD::INTRINSIC_W_CHAIN ||
45504529
Opcode == ISD::INTRINSIC_VOID) {
4551-
// TODO: This can probably be removed once target code is audited. This
4552-
// is here purely to reduce patch size and review complexity.
4553-
if (!VT.isScalableVector()) {
4554-
unsigned NumBits =
4530+
unsigned NumBits =
45554531
TLI->ComputeNumSignBitsForTargetNode(Op, DemandedElts, *this, Depth);
4556-
if (NumBits > 1)
4557-
FirstAnswer = std::max(FirstAnswer, NumBits);
4558-
}
4532+
if (NumBits > 1)
4533+
FirstAnswer = std::max(FirstAnswer, NumBits);
45594534
}
45604535

45614536
// Finally, if we can prove that the top bits of the result are 0's or 1's,

‎llvm/test/CodeGen/AArch64/sve-masked-gather-legalize.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -95,7 +95,7 @@ define <vscale x 2 x float> @masked_gather_nxv2f32(float* %base, <vscale x 2 x i
9595
; CHECK: // %bb.0:
9696
; CHECK-NEXT: ptrue p1.d
9797
; CHECK-NEXT: sxth z0.d, p1/m, z0.d
98-
; CHECK-NEXT: ld1w { z0.d }, p0/z, [x0, z0.d, lsl #2]
98+
; CHECK-NEXT: ld1w { z0.d }, p0/z, [x0, z0.d, sxtw #2]
9999
; CHECK-NEXT: ret
100100
%ptrs = getelementptr float, float* %base, <vscale x 2 x i16> %indices
101101
%data = call <vscale x 2 x float> @llvm.masked.gather.nxv2f32(<vscale x 2 x float*> %ptrs, i32 1, <vscale x 2 x i1> %mask, <vscale x 2 x float> undef)

‎llvm/test/CodeGen/AArch64/sve-smulo-sdnode.ll

Lines changed: 48 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -9,10 +9,15 @@ define <vscale x 2 x i8> @smulo_nxv2i8(<vscale x 2 x i8> %x, <vscale x 2 x i8> %
99
; CHECK-NEXT: ptrue p0.d
1010
; CHECK-NEXT: sxtb z1.d, p0/m, z1.d
1111
; CHECK-NEXT: sxtb z0.d, p0/m, z0.d
12+
; CHECK-NEXT: movprfx z2, z0
13+
; CHECK-NEXT: smulh z2.d, p0/m, z2.d, z1.d
1214
; CHECK-NEXT: mul z0.d, p0/m, z0.d, z1.d
13-
; CHECK-NEXT: movprfx z1, z0
14-
; CHECK-NEXT: sxtb z1.d, p0/m, z0.d
15-
; CHECK-NEXT: cmpne p0.d, p0/z, z1.d, z0.d
15+
; CHECK-NEXT: asr z1.d, z0.d, #63
16+
; CHECK-NEXT: movprfx z3, z0
17+
; CHECK-NEXT: sxtb z3.d, p0/m, z0.d
18+
; CHECK-NEXT: cmpne p1.d, p0/z, z2.d, z1.d
19+
; CHECK-NEXT: cmpne p0.d, p0/z, z3.d, z0.d
20+
; CHECK-NEXT: sel p0.b, p0, p0.b, p1.b
1621
; CHECK-NEXT: mov z0.d, p0/m, #0 // =0x0
1722
; CHECK-NEXT: ret
1823
%a = call { <vscale x 2 x i8>, <vscale x 2 x i1> } @llvm.smul.with.overflow.nxv2i8(<vscale x 2 x i8> %x, <vscale x 2 x i8> %y)
@@ -30,10 +35,15 @@ define <vscale x 4 x i8> @smulo_nxv4i8(<vscale x 4 x i8> %x, <vscale x 4 x i8> %
3035
; CHECK-NEXT: ptrue p0.s
3136
; CHECK-NEXT: sxtb z1.s, p0/m, z1.s
3237
; CHECK-NEXT: sxtb z0.s, p0/m, z0.s
38+
; CHECK-NEXT: movprfx z2, z0
39+
; CHECK-NEXT: smulh z2.s, p0/m, z2.s, z1.s
3340
; CHECK-NEXT: mul z0.s, p0/m, z0.s, z1.s
34-
; CHECK-NEXT: movprfx z1, z0
35-
; CHECK-NEXT: sxtb z1.s, p0/m, z0.s
36-
; CHECK-NEXT: cmpne p0.s, p0/z, z1.s, z0.s
41+
; CHECK-NEXT: asr z1.s, z0.s, #31
42+
; CHECK-NEXT: movprfx z3, z0
43+
; CHECK-NEXT: sxtb z3.s, p0/m, z0.s
44+
; CHECK-NEXT: cmpne p1.s, p0/z, z2.s, z1.s
45+
; CHECK-NEXT: cmpne p0.s, p0/z, z3.s, z0.s
46+
; CHECK-NEXT: sel p0.b, p0, p0.b, p1.b
3747
; CHECK-NEXT: mov z0.s, p0/m, #0 // =0x0
3848
; CHECK-NEXT: ret
3949
%a = call { <vscale x 4 x i8>, <vscale x 4 x i1> } @llvm.smul.with.overflow.nxv4i8(<vscale x 4 x i8> %x, <vscale x 4 x i8> %y)
@@ -51,10 +61,15 @@ define <vscale x 8 x i8> @smulo_nxv8i8(<vscale x 8 x i8> %x, <vscale x 8 x i8> %
5161
; CHECK-NEXT: ptrue p0.h
5262
; CHECK-NEXT: sxtb z1.h, p0/m, z1.h
5363
; CHECK-NEXT: sxtb z0.h, p0/m, z0.h
64+
; CHECK-NEXT: movprfx z2, z0
65+
; CHECK-NEXT: smulh z2.h, p0/m, z2.h, z1.h
5466
; CHECK-NEXT: mul z0.h, p0/m, z0.h, z1.h
55-
; CHECK-NEXT: movprfx z1, z0
56-
; CHECK-NEXT: sxtb z1.h, p0/m, z0.h
57-
; CHECK-NEXT: cmpne p0.h, p0/z, z1.h, z0.h
67+
; CHECK-NEXT: asr z1.h, z0.h, #15
68+
; CHECK-NEXT: movprfx z3, z0
69+
; CHECK-NEXT: sxtb z3.h, p0/m, z0.h
70+
; CHECK-NEXT: cmpne p1.h, p0/z, z2.h, z1.h
71+
; CHECK-NEXT: cmpne p0.h, p0/z, z3.h, z0.h
72+
; CHECK-NEXT: sel p0.b, p0, p0.b, p1.b
5873
; CHECK-NEXT: mov z0.h, p0/m, #0 // =0x0
5974
; CHECK-NEXT: ret
6075
%a = call { <vscale x 8 x i8>, <vscale x 8 x i1> } @llvm.smul.with.overflow.nxv8i8(<vscale x 8 x i8> %x, <vscale x 8 x i8> %y)
@@ -160,10 +175,15 @@ define <vscale x 2 x i16> @smulo_nxv2i16(<vscale x 2 x i16> %x, <vscale x 2 x i1
160175
; CHECK-NEXT: ptrue p0.d
161176
; CHECK-NEXT: sxth z1.d, p0/m, z1.d
162177
; CHECK-NEXT: sxth z0.d, p0/m, z0.d
178+
; CHECK-NEXT: movprfx z2, z0
179+
; CHECK-NEXT: smulh z2.d, p0/m, z2.d, z1.d
163180
; CHECK-NEXT: mul z0.d, p0/m, z0.d, z1.d
164-
; CHECK-NEXT: movprfx z1, z0
165-
; CHECK-NEXT: sxth z1.d, p0/m, z0.d
166-
; CHECK-NEXT: cmpne p0.d, p0/z, z1.d, z0.d
181+
; CHECK-NEXT: asr z1.d, z0.d, #63
182+
; CHECK-NEXT: movprfx z3, z0
183+
; CHECK-NEXT: sxth z3.d, p0/m, z0.d
184+
; CHECK-NEXT: cmpne p1.d, p0/z, z2.d, z1.d
185+
; CHECK-NEXT: cmpne p0.d, p0/z, z3.d, z0.d
186+
; CHECK-NEXT: sel p0.b, p0, p0.b, p1.b
167187
; CHECK-NEXT: mov z0.d, p0/m, #0 // =0x0
168188
; CHECK-NEXT: ret
169189
%a = call { <vscale x 2 x i16>, <vscale x 2 x i1> } @llvm.smul.with.overflow.nxv2i16(<vscale x 2 x i16> %x, <vscale x 2 x i16> %y)
@@ -181,10 +201,15 @@ define <vscale x 4 x i16> @smulo_nxv4i16(<vscale x 4 x i16> %x, <vscale x 4 x i1
181201
; CHECK-NEXT: ptrue p0.s
182202
; CHECK-NEXT: sxth z1.s, p0/m, z1.s
183203
; CHECK-NEXT: sxth z0.s, p0/m, z0.s
204+
; CHECK-NEXT: movprfx z2, z0
205+
; CHECK-NEXT: smulh z2.s, p0/m, z2.s, z1.s
184206
; CHECK-NEXT: mul z0.s, p0/m, z0.s, z1.s
185-
; CHECK-NEXT: movprfx z1, z0
186-
; CHECK-NEXT: sxth z1.s, p0/m, z0.s
187-
; CHECK-NEXT: cmpne p0.s, p0/z, z1.s, z0.s
207+
; CHECK-NEXT: asr z1.s, z0.s, #31
208+
; CHECK-NEXT: movprfx z3, z0
209+
; CHECK-NEXT: sxth z3.s, p0/m, z0.s
210+
; CHECK-NEXT: cmpne p1.s, p0/z, z2.s, z1.s
211+
; CHECK-NEXT: cmpne p0.s, p0/z, z3.s, z0.s
212+
; CHECK-NEXT: sel p0.b, p0, p0.b, p1.b
188213
; CHECK-NEXT: mov z0.s, p0/m, #0 // =0x0
189214
; CHECK-NEXT: ret
190215
%a = call { <vscale x 4 x i16>, <vscale x 4 x i1> } @llvm.smul.with.overflow.nxv4i16(<vscale x 4 x i16> %x, <vscale x 4 x i16> %y)
@@ -290,10 +315,15 @@ define <vscale x 2 x i32> @smulo_nxv2i32(<vscale x 2 x i32> %x, <vscale x 2 x i3
290315
; CHECK-NEXT: ptrue p0.d
291316
; CHECK-NEXT: sxtw z1.d, p0/m, z1.d
292317
; CHECK-NEXT: sxtw z0.d, p0/m, z0.d
318+
; CHECK-NEXT: movprfx z2, z0
319+
; CHECK-NEXT: smulh z2.d, p0/m, z2.d, z1.d
293320
; CHECK-NEXT: mul z0.d, p0/m, z0.d, z1.d
294-
; CHECK-NEXT: movprfx z1, z0
295-
; CHECK-NEXT: sxtw z1.d, p0/m, z0.d
296-
; CHECK-NEXT: cmpne p0.d, p0/z, z1.d, z0.d
321+
; CHECK-NEXT: asr z1.d, z0.d, #63
322+
; CHECK-NEXT: movprfx z3, z0
323+
; CHECK-NEXT: sxtw z3.d, p0/m, z0.d
324+
; CHECK-NEXT: cmpne p1.d, p0/z, z2.d, z1.d
325+
; CHECK-NEXT: cmpne p0.d, p0/z, z3.d, z0.d
326+
; CHECK-NEXT: sel p0.b, p0, p0.b, p1.b
297327
; CHECK-NEXT: mov z0.d, p0/m, #0 // =0x0
298328
; CHECK-NEXT: ret
299329
%a = call { <vscale x 2 x i32>, <vscale x 2 x i1> } @llvm.smul.with.overflow.nxv2i32(<vscale x 2 x i32> %x, <vscale x 2 x i32> %y)

‎llvm/test/CodeGen/RISCV/rvv/vdiv-vp.ll

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -12,8 +12,11 @@ define <vscale x 8 x i7> @vdiv_vx_nxv8i7(<vscale x 8 x i7> %a, i7 signext %b, <v
1212
; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, ma
1313
; CHECK-NEXT: vadd.vv v8, v8, v8
1414
; CHECK-NEXT: vsra.vi v8, v8, 1
15+
; CHECK-NEXT: vmv.v.x v9, a0
16+
; CHECK-NEXT: vadd.vv v9, v9, v9
17+
; CHECK-NEXT: vsra.vi v9, v9, 1
1518
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma
16-
; CHECK-NEXT: vdiv.vx v8, v8, a0, v0.t
19+
; CHECK-NEXT: vdiv.vv v8, v8, v9, v0.t
1720
; CHECK-NEXT: ret
1821
%elt.head = insertelement <vscale x 8 x i7> poison, i7 %b, i32 0
1922
%vb = shufflevector <vscale x 8 x i7> %elt.head, <vscale x 8 x i7> poison, <vscale x 8 x i32> zeroinitializer

‎llvm/test/CodeGen/RISCV/rvv/vmax-vp.ll

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -12,8 +12,11 @@ define <vscale x 8 x i7> @vmax_vx_nxv8i7(<vscale x 8 x i7> %a, i7 signext %b, <v
1212
; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, ma
1313
; CHECK-NEXT: vadd.vv v8, v8, v8
1414
; CHECK-NEXT: vsra.vi v8, v8, 1
15+
; CHECK-NEXT: vmv.v.x v9, a0
16+
; CHECK-NEXT: vadd.vv v9, v9, v9
17+
; CHECK-NEXT: vsra.vi v9, v9, 1
1518
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma
16-
; CHECK-NEXT: vmax.vx v8, v8, a0, v0.t
19+
; CHECK-NEXT: vmax.vv v8, v8, v9, v0.t
1720
; CHECK-NEXT: ret
1821
%elt.head = insertelement <vscale x 8 x i7> poison, i7 %b, i32 0
1922
%vb = shufflevector <vscale x 8 x i7> %elt.head, <vscale x 8 x i7> poison, <vscale x 8 x i32> zeroinitializer

‎llvm/test/CodeGen/RISCV/rvv/vmin-vp.ll

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -12,8 +12,11 @@ define <vscale x 8 x i7> @vmin_vx_nxv8i7(<vscale x 8 x i7> %a, i7 signext %b, <v
1212
; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, ma
1313
; CHECK-NEXT: vadd.vv v8, v8, v8
1414
; CHECK-NEXT: vsra.vi v8, v8, 1
15+
; CHECK-NEXT: vmv.v.x v9, a0
16+
; CHECK-NEXT: vadd.vv v9, v9, v9
17+
; CHECK-NEXT: vsra.vi v9, v9, 1
1518
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma
16-
; CHECK-NEXT: vmin.vx v8, v8, a0, v0.t
19+
; CHECK-NEXT: vmin.vv v8, v8, v9, v0.t
1720
; CHECK-NEXT: ret
1821
%elt.head = insertelement <vscale x 8 x i7> poison, i7 %b, i32 0
1922
%vb = shufflevector <vscale x 8 x i7> %elt.head, <vscale x 8 x i7> poison, <vscale x 8 x i32> zeroinitializer

‎llvm/test/CodeGen/RISCV/rvv/vrem-vp.ll

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -12,8 +12,11 @@ define <vscale x 8 x i7> @vrem_vx_nxv8i7(<vscale x 8 x i7> %a, i7 signext %b, <v
1212
; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, ma
1313
; CHECK-NEXT: vadd.vv v8, v8, v8
1414
; CHECK-NEXT: vsra.vi v8, v8, 1
15+
; CHECK-NEXT: vmv.v.x v9, a0
16+
; CHECK-NEXT: vadd.vv v9, v9, v9
17+
; CHECK-NEXT: vsra.vi v9, v9, 1
1518
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma
16-
; CHECK-NEXT: vrem.vx v8, v8, a0, v0.t
19+
; CHECK-NEXT: vrem.vv v8, v8, v9, v0.t
1720
; CHECK-NEXT: ret
1821
%elt.head = insertelement <vscale x 8 x i7> poison, i7 %b, i32 0
1922
%vb = shufflevector <vscale x 8 x i7> %elt.head, <vscale x 8 x i7> poison, <vscale x 8 x i32> zeroinitializer

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