@@ -1506,19 +1506,49 @@ static bool isUnsupportedAMDGPUAddrspace(Value *Addr) {
1506
1506
return false ;
1507
1507
}
1508
1508
1509
- static bool isUnsupportedSPIRAccess (Value *Addr, Function *Func) {
1509
+ static bool containsTargetExtType (const Type *Ty) {
1510
+ if (isa<TargetExtType>(Ty))
1511
+ return true ;
1512
+
1513
+ if (Ty->isVectorTy ())
1514
+ return containsTargetExtType (Ty->getScalarType ());
1515
+
1516
+ if (Ty->isArrayTy ())
1517
+ return containsTargetExtType (Ty->getArrayElementType ());
1518
+
1519
+ if (auto *STy = dyn_cast<StructType>(Ty)) {
1520
+ for (unsigned int i = 0 ; i < STy->getNumElements (); i++)
1521
+ if (containsTargetExtType (STy->getElementType (i)))
1522
+ return true ;
1523
+ return false ;
1524
+ }
1525
+
1526
+ return false ;
1527
+ }
1528
+
1529
+ static bool isUnsupportedSPIRAccess (Value *Addr, Instruction *Inst) {
1510
1530
// Skip SPIR-V built-in varibles
1511
1531
auto *OrigValue = Addr->stripInBoundsOffsets ();
1512
1532
if (OrigValue->getName ().starts_with (" __spirv_BuiltIn" ))
1513
1533
return true ;
1514
1534
1535
+ // Ignore load/store for target ext type since we can't know exactly what size
1536
+ // it is.
1537
+ if (isa<StoreInst>(Inst) &&
1538
+ containsTargetExtType (
1539
+ cast<StoreInst>(Inst)->getValueOperand ()->getType ()))
1540
+ return true ;
1541
+
1542
+ if (isa<LoadInst>(Inst) && containsTargetExtType (Inst->getType ()))
1543
+ return true ;
1544
+
1515
1545
Type *PtrTy = cast<PointerType>(Addr->getType ()->getScalarType ());
1516
1546
switch (PtrTy->getPointerAddressSpace ()) {
1517
1547
case kSpirOffloadPrivateAS : {
1518
1548
if (!ClSpirOffloadPrivates)
1519
1549
return true ;
1520
1550
// Skip kernel arguments
1521
- return Func ->getCallingConv () == CallingConv::SPIR_KERNEL &&
1551
+ return Inst-> getFunction () ->getCallingConv () == CallingConv::SPIR_KERNEL &&
1522
1552
isa<Argument>(Addr);
1523
1553
}
1524
1554
case kSpirOffloadGlobalAS : {
@@ -1756,7 +1786,10 @@ bool AddressSanitizer::isInterestingAlloca(const AllocaInst &AI) {
1756
1786
// swifterror allocas are register promoted by ISel
1757
1787
!AI.isSwiftError () &&
1758
1788
// safe allocas are not interesting
1759
- !(SSGI && SSGI->isSafe (AI)));
1789
+ !(SSGI && SSGI->isSafe (AI)) &&
1790
+ // ignore alloc contains target ext type since we can't know exactly what
1791
+ // size it is.
1792
+ !containsTargetExtType (AI.getAllocatedType ()));
1760
1793
1761
1794
ProcessedAllocas[&AI] = IsInteresting;
1762
1795
return IsInteresting;
@@ -1765,7 +1798,7 @@ bool AddressSanitizer::isInterestingAlloca(const AllocaInst &AI) {
1765
1798
bool AddressSanitizer::ignoreAccess (Instruction *Inst, Value *Ptr) {
1766
1799
// SPIR has its own rules to filter the instrument accesses
1767
1800
if (TargetTriple.isSPIROrSPIRV ()) {
1768
- if (isUnsupportedSPIRAccess (Ptr, Inst-> getFunction () ))
1801
+ if (isUnsupportedSPIRAccess (Ptr, Inst))
1769
1802
return true ;
1770
1803
} else {
1771
1804
// Instrument accesses from different address spaces only for AMDGPU.
0 commit comments