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Merge tag 'drm-fixes-2025-04-26' of https://gitlab.freedesktop.org/drm/kernel
Pull drm fixes from Dave Airlie: "Weekly drm fixes, mostly amdgpu, with some exynos cleanups and a couple of minor fixes, seems a bit quiet, but probably some lag from Easter holidays. amdgpu: - P2P DMA fixes - Display reset fixes - DCN 3.5 fixes - ACPI EDID fix - LTTPR fix - mode_valid() fix exynos: - fix spelling error - remove redundant error handling in exynos_drm_vidi.c module - marks struct decon_data as const in the exynos7_drm_decon driver since it is only read - Remove unnecessary checking in exynos_drm_drv.c module meson: - Fix VCLK calculation panel: - jd9365a: Fix reset polarity" * tag 'drm-fixes-2025-04-26' of https://gitlab.freedesktop.org/drm/kernel: drm/exynos: Fix spelling mistake "enqueu" -> "enqueue" drm/exynos: exynos7_drm_decon: Consstify struct decon_data drm/exynos: fixed a spelling error drm/exynos/vidi: Remove redundant error handling in vidi_get_modes() drm/exynos: Remove unnecessary checking drm/amd/display: do not copy invalid CRTC timing info drm/amd/display: Default IPS to RCG_IN_ACTIVE_IPS2_IN_OFF drm/amd/display: Use 16ms AUX read interval for LTTPR with old sinks drm/amd/display: Fix ACPI edid parsing on some Lenovo systems drm/amdgpu: Allow P2P access through XGMI drm/amd/display: Enable urgent latency adjustment on DCN35 drm/amd/display: Force full update in gpu reset drm/amd/display: Fix gpu reset in multidisplay config drm/amdgpu: Don't pin VRAM without DMABUF_MOVE_NOTIFY drm/amdgpu: Use allowed_domains for pinning dmabufs drm: panel: jd9365da: fix reset signal polarity in unprepare drm/meson: use unsigned long long / Hz for frequency types Revert "drm/meson: vclk: fix calculation of 59.94 fractional rates"
2 parents f1a3944 + 250130d commit fa573ae

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16 files changed

+229
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lines changed

‎drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c

Lines changed: 45 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -43,6 +43,29 @@
4343
#include <linux/dma-fence-array.h>
4444
#include <linux/pci-p2pdma.h>
4545

46+
static const struct dma_buf_attach_ops amdgpu_dma_buf_attach_ops;
47+
48+
/**
49+
* dma_buf_attach_adev - Helper to get adev of an attachment
50+
*
51+
* @attach: attachment
52+
*
53+
* Returns:
54+
* A struct amdgpu_device * if the attaching device is an amdgpu device or
55+
* partition, NULL otherwise.
56+
*/
57+
static struct amdgpu_device *dma_buf_attach_adev(struct dma_buf_attachment *attach)
58+
{
59+
if (attach->importer_ops == &amdgpu_dma_buf_attach_ops) {
60+
struct drm_gem_object *obj = attach->importer_priv;
61+
struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
62+
63+
return amdgpu_ttm_adev(bo->tbo.bdev);
64+
}
65+
66+
return NULL;
67+
}
68+
4669
/**
4770
* amdgpu_dma_buf_attach - &dma_buf_ops.attach implementation
4871
*
@@ -54,11 +77,13 @@
5477
static int amdgpu_dma_buf_attach(struct dma_buf *dmabuf,
5578
struct dma_buf_attachment *attach)
5679
{
80+
struct amdgpu_device *attach_adev = dma_buf_attach_adev(attach);
5781
struct drm_gem_object *obj = dmabuf->priv;
5882
struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
5983
struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
6084

61-
if (pci_p2pdma_distance(adev->pdev, attach->dev, false) < 0)
85+
if (!amdgpu_dmabuf_is_xgmi_accessible(attach_adev, bo) &&
86+
pci_p2pdma_distance(adev->pdev, attach->dev, false) < 0)
6287
attach->peer2peer = false;
6388

6489
amdgpu_vm_bo_update_shared(bo);
@@ -77,22 +102,32 @@ static int amdgpu_dma_buf_pin(struct dma_buf_attachment *attach)
77102
{
78103
struct dma_buf *dmabuf = attach->dmabuf;
79104
struct amdgpu_bo *bo = gem_to_amdgpu_bo(dmabuf->priv);
80-
u32 domains = bo->preferred_domains;
105+
u32 domains = bo->allowed_domains;
81106

82107
dma_resv_assert_held(dmabuf->resv);
83108

84-
/*
85-
* Try pinning into VRAM to allow P2P with RDMA NICs without ODP
109+
/* Try pinning into VRAM to allow P2P with RDMA NICs without ODP
86110
* support if all attachments can do P2P. If any attachment can't do
87111
* P2P just pin into GTT instead.
112+
*
113+
* To avoid with conflicting pinnings between GPUs and RDMA when move
114+
* notifiers are disabled, only allow pinning in VRAM when move
115+
* notiers are enabled.
88116
*/
89-
list_for_each_entry(attach, &dmabuf->attachments, node)
90-
if (!attach->peer2peer)
91-
domains &= ~AMDGPU_GEM_DOMAIN_VRAM;
117+
if (!IS_ENABLED(CONFIG_DMABUF_MOVE_NOTIFY)) {
118+
domains &= ~AMDGPU_GEM_DOMAIN_VRAM;
119+
} else {
120+
list_for_each_entry(attach, &dmabuf->attachments, node)
121+
if (!attach->peer2peer)
122+
domains &= ~AMDGPU_GEM_DOMAIN_VRAM;
123+
}
92124

93125
if (domains & AMDGPU_GEM_DOMAIN_VRAM)
94126
bo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
95127

128+
if (WARN_ON(!domains))
129+
return -EINVAL;
130+
96131
return amdgpu_bo_pin(bo, domains);
97132
}
98133

@@ -470,6 +505,9 @@ bool amdgpu_dmabuf_is_xgmi_accessible(struct amdgpu_device *adev,
470505
struct drm_gem_object *obj = &bo->tbo.base;
471506
struct drm_gem_object *gobj;
472507

508+
if (!adev)
509+
return false;
510+
473511
if (obj->import_attach) {
474512
struct dma_buf *dma_buf = obj->import_attach->dmabuf;
475513

‎drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

Lines changed: 12 additions & 29 deletions
Original file line numberDiff line numberDiff line change
@@ -1920,26 +1920,6 @@ static enum dmub_ips_disable_type dm_get_default_ips_mode(
19201920
switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {
19211921
case IP_VERSION(3, 5, 0):
19221922
case IP_VERSION(3, 6, 0):
1923-
/*
1924-
* On DCN35 systems with Z8 enabled, it's possible for IPS2 + Z8 to
1925-
* cause a hard hang. A fix exists for newer PMFW.
1926-
*
1927-
* As a workaround, for non-fixed PMFW, force IPS1+RCG as the deepest
1928-
* IPS state in all cases, except for s0ix and all displays off (DPMS),
1929-
* where IPS2 is allowed.
1930-
*
1931-
* When checking pmfw version, use the major and minor only.
1932-
*/
1933-
if ((adev->pm.fw_version & 0x00FFFF00) < 0x005D6300)
1934-
ret = DMUB_IPS_RCG_IN_ACTIVE_IPS2_IN_OFF;
1935-
else if (amdgpu_ip_version(adev, GC_HWIP, 0) > IP_VERSION(11, 5, 0))
1936-
/*
1937-
* Other ASICs with DCN35 that have residency issues with
1938-
* IPS2 in idle.
1939-
* We want them to use IPS2 only in display off cases.
1940-
*/
1941-
ret = DMUB_IPS_RCG_IN_ACTIVE_IPS2_IN_OFF;
1942-
break;
19431923
case IP_VERSION(3, 5, 1):
19441924
ret = DMUB_IPS_RCG_IN_ACTIVE_IPS2_IN_OFF;
19451925
break;
@@ -3355,16 +3335,16 @@ static void dm_gpureset_commit_state(struct dc_state *dc_state,
33553335
for (k = 0; k < dc_state->stream_count; k++) {
33563336
bundle->stream_update.stream = dc_state->streams[k];
33573337

3358-
for (m = 0; m < dc_state->stream_status->plane_count; m++) {
3338+
for (m = 0; m < dc_state->stream_status[k].plane_count; m++) {
33593339
bundle->surface_updates[m].surface =
3360-
dc_state->stream_status->plane_states[m];
3340+
dc_state->stream_status[k].plane_states[m];
33613341
bundle->surface_updates[m].surface->force_full_update =
33623342
true;
33633343
}
33643344

33653345
update_planes_and_stream_adapter(dm->dc,
33663346
UPDATE_TYPE_FULL,
3367-
dc_state->stream_status->plane_count,
3347+
dc_state->stream_status[k].plane_count,
33683348
dc_state->streams[k],
33693349
&bundle->stream_update,
33703350
bundle->surface_updates);
@@ -6521,12 +6501,12 @@ decide_crtc_timing_for_drm_display_mode(struct drm_display_mode *drm_mode,
65216501
const struct drm_display_mode *native_mode,
65226502
bool scale_enabled)
65236503
{
6524-
if (scale_enabled) {
6525-
copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
6526-
} else if (native_mode->clock == drm_mode->clock &&
6527-
native_mode->htotal == drm_mode->htotal &&
6528-
native_mode->vtotal == drm_mode->vtotal) {
6529-
copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
6504+
if (scale_enabled || (
6505+
native_mode->clock == drm_mode->clock &&
6506+
native_mode->htotal == drm_mode->htotal &&
6507+
native_mode->vtotal == drm_mode->vtotal)) {
6508+
if (native_mode->crtc_clock)
6509+
copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
65306510
} else {
65316511
/* no scaling nor amdgpu inserted, no need to patch */
65326512
}
@@ -11043,6 +11023,9 @@ static bool should_reset_plane(struct drm_atomic_state *state,
1104311023
state->allow_modeset)
1104411024
return true;
1104511025

11026+
if (amdgpu_in_reset(adev) && state->allow_modeset)
11027+
return true;
11028+
1104611029
/* Exit early if we know that we're adding or removing the plane. */
1104711030
if (old_plane_state->crtc != new_plane_state->crtc)
1104811031
return true;

‎drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -918,7 +918,7 @@ dm_helpers_probe_acpi_edid(void *data, u8 *buf, unsigned int block, size_t len)
918918
{
919919
struct drm_connector *connector = data;
920920
struct acpi_device *acpidev = ACPI_COMPANION(connector->dev->dev);
921-
unsigned char start = block * EDID_LENGTH;
921+
unsigned short start = block * EDID_LENGTH;
922922
struct edid *edid;
923923
int r;
924924

‎drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -195,9 +195,9 @@ struct _vcs_dpi_soc_bounding_box_st dcn3_5_soc = {
195195
.dcn_downspread_percent = 0.5,
196196
.gpuvm_min_page_size_bytes = 4096,
197197
.hostvm_min_page_size_bytes = 4096,
198-
.do_urgent_latency_adjustment = 0,
198+
.do_urgent_latency_adjustment = 1,
199199
.urgent_latency_adjustment_fabric_clock_component_us = 0,
200-
.urgent_latency_adjustment_fabric_clock_reference_mhz = 0,
200+
.urgent_latency_adjustment_fabric_clock_reference_mhz = 3000,
201201
};
202202

203203
void dcn35_build_wm_range_table_fpu(struct clk_mgr *clk_mgr)

‎drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_8b_10b.c

Lines changed: 36 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -35,6 +35,17 @@
3535
#define DC_LOGGER \
3636
link->ctx->logger
3737

38+
static void get_default_8b_10b_lttpr_aux_rd_interval(
39+
union training_aux_rd_interval *training_rd_interval)
40+
{
41+
/* LTTPR are required to program DPCD 0000Eh to 0x4 (16ms) upon AUX
42+
* read reply to this register. Since old sinks with DPCD rev 1.1
43+
* and earlier may not support this register, assume the mandatory
44+
* value is programmed by the LTTPR to avoid AUX timeout issues.
45+
*/
46+
training_rd_interval->raw = 0x4;
47+
}
48+
3849
static int32_t get_cr_training_aux_rd_interval(struct dc_link *link,
3950
const struct dc_link_settings *link_settings,
4051
enum lttpr_mode lttpr_mode)
@@ -43,17 +54,22 @@ static int32_t get_cr_training_aux_rd_interval(struct dc_link *link,
4354
uint32_t wait_in_micro_secs = 100;
4455

4556
memset(&training_rd_interval, 0, sizeof(training_rd_interval));
46-
if (link_dp_get_encoding_format(link_settings) == DP_8b_10b_ENCODING &&
47-
link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_12) {
48-
core_link_read_dpcd(
49-
link,
50-
DP_TRAINING_AUX_RD_INTERVAL,
51-
(uint8_t *)&training_rd_interval,
52-
sizeof(training_rd_interval));
53-
if (lttpr_mode != LTTPR_MODE_NON_TRANSPARENT)
54-
wait_in_micro_secs = 400;
55-
if (training_rd_interval.bits.TRAINIG_AUX_RD_INTERVAL)
56-
wait_in_micro_secs = training_rd_interval.bits.TRAINIG_AUX_RD_INTERVAL * 4000;
57+
if (link_dp_get_encoding_format(link_settings) == DP_8b_10b_ENCODING) {
58+
if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_12)
59+
core_link_read_dpcd(
60+
link,
61+
DP_TRAINING_AUX_RD_INTERVAL,
62+
(uint8_t *)&training_rd_interval,
63+
sizeof(training_rd_interval));
64+
else if (dp_is_lttpr_present(link))
65+
get_default_8b_10b_lttpr_aux_rd_interval(&training_rd_interval);
66+
67+
if (training_rd_interval.raw != 0) {
68+
if (lttpr_mode != LTTPR_MODE_NON_TRANSPARENT)
69+
wait_in_micro_secs = 400;
70+
if (training_rd_interval.bits.TRAINIG_AUX_RD_INTERVAL)
71+
wait_in_micro_secs = training_rd_interval.bits.TRAINIG_AUX_RD_INTERVAL * 4000;
72+
}
5773
}
5874
return wait_in_micro_secs;
5975
}
@@ -71,13 +87,15 @@ static uint32_t get_eq_training_aux_rd_interval(
7187
DP_128B132B_TRAINING_AUX_RD_INTERVAL,
7288
(uint8_t *)&training_rd_interval,
7389
sizeof(training_rd_interval));
74-
} else if (link_dp_get_encoding_format(link_settings) == DP_8b_10b_ENCODING &&
75-
link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_12) {
76-
core_link_read_dpcd(
77-
link,
78-
DP_TRAINING_AUX_RD_INTERVAL,
79-
(uint8_t *)&training_rd_interval,
80-
sizeof(training_rd_interval));
90+
} else if (link_dp_get_encoding_format(link_settings) == DP_8b_10b_ENCODING) {
91+
if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_12)
92+
core_link_read_dpcd(
93+
link,
94+
DP_TRAINING_AUX_RD_INTERVAL,
95+
(uint8_t *)&training_rd_interval,
96+
sizeof(training_rd_interval));
97+
else if (dp_is_lttpr_present(link))
98+
get_default_8b_10b_lttpr_aux_rd_interval(&training_rd_interval);
8199
}
82100

83101
switch (training_rd_interval.bits.TRAINIG_AUX_RD_INTERVAL) {

‎drivers/gpu/drm/exynos/exynos7_drm_decon.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -43,13 +43,13 @@ struct decon_data {
4343
unsigned int wincon_burstlen_shift;
4444
};
4545

46-
static struct decon_data exynos7_decon_data = {
46+
static const struct decon_data exynos7_decon_data = {
4747
.vidw_buf_start_base = 0x80,
4848
.shadowcon_win_protect_shift = 10,
4949
.wincon_burstlen_shift = 11,
5050
};
5151

52-
static struct decon_data exynos7870_decon_data = {
52+
static const struct decon_data exynos7870_decon_data = {
5353
.vidw_buf_start_base = 0x880,
5454
.shadowcon_win_protect_shift = 8,
5555
.wincon_burstlen_shift = 10,

‎drivers/gpu/drm/exynos/exynos_drm_drv.c

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -355,8 +355,7 @@ static void exynos_drm_platform_shutdown(struct platform_device *pdev)
355355
{
356356
struct drm_device *drm = platform_get_drvdata(pdev);
357357

358-
if (drm)
359-
drm_atomic_helper_shutdown(drm);
358+
drm_atomic_helper_shutdown(drm);
360359
}
361360

362361
static struct platform_driver exynos_drm_platform_driver = {

‎drivers/gpu/drm/exynos/exynos_drm_fimc.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -908,7 +908,7 @@ static void fimc_dst_set_buf_seq(struct fimc_context *ctx, u32 buf_id,
908908
u32 buf_num;
909909
u32 cfg;
910910

911-
DRM_DEV_DEBUG_KMS(ctx->dev, "buf_id[%d]enqueu[%d]\n", buf_id, enqueue);
911+
DRM_DEV_DEBUG_KMS(ctx->dev, "buf_id[%d]enqueue[%d]\n", buf_id, enqueue);
912912

913913
spin_lock_irqsave(&ctx->lock, flags);
914914

‎drivers/gpu/drm/exynos/exynos_drm_fimd.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -731,7 +731,7 @@ static void fimd_win_set_pixfmt(struct fimd_context *ctx, unsigned int win,
731731
/*
732732
* Setting dma-burst to 16Word causes permanent tearing for very small
733733
* buffers, e.g. cursor buffer. Burst Mode switching which based on
734-
* plane size is not recommended as plane size varies alot towards the
734+
* plane size is not recommended as plane size varies a lot towards the
735735
* end of the screen and rapid movement causes unstable DMA, but it is
736736
* still better to change dma-burst than displaying garbage.
737737
*/

‎drivers/gpu/drm/exynos/exynos_drm_vidi.c

Lines changed: 0 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -312,9 +312,6 @@ static int vidi_get_modes(struct drm_connector *connector)
312312
else
313313
drm_edid = drm_edid_alloc(fake_edid_info, sizeof(fake_edid_info));
314314

315-
if (!drm_edid)
316-
return 0;
317-
318315
drm_edid_connector_update(connector, drm_edid);
319316

320317
count = drm_edid_connector_add_modes(connector);

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