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prabhakarladgeertu
prabhakarlad
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geertu
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clk: renesas: rzv2h: Add support for RZ/V2N SoC
The clock structure for RZ/V2N is almost identical to RZ/V2H(P) SoC with less IP blocks compared to RZ/V2H(P). For eg: CRU2/3 are present only on the RZ/V2H(P) SoC. Add minimal clock and reset entries required to boot the Renesas RZ/V2N EVK and binds it with the RZ/V2H CPG family driver. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250407191628.323613-9-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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‎drivers/clk/renesas/Kconfig

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@@ -41,6 +41,7 @@ config CLK_RENESAS
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select CLK_R9A08G045 if ARCH_R9A08G045
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select CLK_R9A09G011 if ARCH_R9A09G011
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select CLK_R9A09G047 if ARCH_R9A09G047
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select CLK_R9A09G056 if ARCH_R9A09G056
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select CLK_R9A09G057 if ARCH_R9A09G057
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select CLK_SH73A0 if ARCH_SH73A0
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@@ -199,6 +200,10 @@ config CLK_R9A09G047
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bool "RZ/G3E clock support" if COMPILE_TEST
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select CLK_RZV2H
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config CLK_R9A09G056
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bool "RZ/V2N clock support" if COMPILE_TEST
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select CLK_RZV2H
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config CLK_R9A09G057
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bool "RZ/V2H(P) clock support" if COMPILE_TEST
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select CLK_RZV2H

‎drivers/clk/renesas/Makefile

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@@ -38,6 +38,7 @@ obj-$(CONFIG_CLK_R9A07G054) += r9a07g044-cpg.o
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obj-$(CONFIG_CLK_R9A08G045) += r9a08g045-cpg.o
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obj-$(CONFIG_CLK_R9A09G011) += r9a09g011-cpg.o
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obj-$(CONFIG_CLK_R9A09G047) += r9a09g047-cpg.o
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obj-$(CONFIG_CLK_R9A09G056) += r9a09g056-cpg.o
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obj-$(CONFIG_CLK_R9A09G057) += r9a09g057-cpg.o
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obj-$(CONFIG_CLK_SH73A0) += clk-sh73a0.o
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‎drivers/clk/renesas/r9a09g056-cpg.c

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@@ -0,0 +1,152 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Renesas RZ/V2N CPG driver
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*
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* Copyright (C) 2025 Renesas Electronics Corp.
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*/
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#include <linux/clk-provider.h>
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#include <linux/device.h>
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <dt-bindings/clock/renesas,r9a09g056-cpg.h>
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#include "rzv2h-cpg.h"
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enum clk_ids {
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/* Core Clock Outputs exported to DT */
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LAST_DT_CORE_CLK = R9A09G056_GBETH_1_CLK_PTP_REF_I,
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/* External Input Clocks */
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CLK_AUDIO_EXTAL,
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CLK_RTXIN,
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CLK_QEXTAL,
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/* PLL Clocks */
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CLK_PLLCM33,
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CLK_PLLCLN,
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CLK_PLLDTY,
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CLK_PLLCA55,
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/* Internal Core Clocks */
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CLK_PLLCM33_DIV16,
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CLK_PLLCLN_DIV2,
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CLK_PLLCLN_DIV8,
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CLK_PLLDTY_ACPU,
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CLK_PLLDTY_ACPU_DIV4,
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/* Module Clocks */
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MOD_CLK_BASE,
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};
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static const struct clk_div_table dtable_1_8[] = {
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{0, 1},
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{1, 2},
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{2, 4},
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{3, 8},
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{0, 0},
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};
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static const struct clk_div_table dtable_2_64[] = {
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{0, 2},
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{1, 4},
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{2, 8},
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{3, 16},
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{4, 64},
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{0, 0},
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};
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static const struct cpg_core_clk r9a09g056_core_clks[] __initconst = {
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/* External Clock Inputs */
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DEF_INPUT("audio_extal", CLK_AUDIO_EXTAL),
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DEF_INPUT("rtxin", CLK_RTXIN),
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DEF_INPUT("qextal", CLK_QEXTAL),
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/* PLL Clocks */
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DEF_FIXED(".pllcm33", CLK_PLLCM33, CLK_QEXTAL, 200, 3),
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DEF_FIXED(".pllcln", CLK_PLLCLN, CLK_QEXTAL, 200, 3),
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DEF_FIXED(".plldty", CLK_PLLDTY, CLK_QEXTAL, 200, 3),
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DEF_PLL(".pllca55", CLK_PLLCA55, CLK_QEXTAL, PLLCA55),
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/* Internal Core Clocks */
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DEF_FIXED(".pllcm33_div16", CLK_PLLCM33_DIV16, CLK_PLLCM33, 1, 16),
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DEF_FIXED(".pllcln_div2", CLK_PLLCLN_DIV2, CLK_PLLCLN, 1, 2),
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DEF_FIXED(".pllcln_div8", CLK_PLLCLN_DIV8, CLK_PLLCLN, 1, 8),
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DEF_DDIV(".plldty_acpu", CLK_PLLDTY_ACPU, CLK_PLLDTY, CDDIV0_DIVCTL2, dtable_2_64),
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DEF_FIXED(".plldty_acpu_div4", CLK_PLLDTY_ACPU_DIV4, CLK_PLLDTY_ACPU, 1, 4),
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/* Core Clocks */
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DEF_FIXED("sys_0_pclk", R9A09G056_SYS_0_PCLK, CLK_QEXTAL, 1, 1),
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DEF_DDIV("ca55_0_coreclk0", R9A09G056_CA55_0_CORE_CLK0, CLK_PLLCA55,
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CDDIV1_DIVCTL0, dtable_1_8),
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DEF_DDIV("ca55_0_coreclk1", R9A09G056_CA55_0_CORE_CLK1, CLK_PLLCA55,
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CDDIV1_DIVCTL1, dtable_1_8),
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DEF_DDIV("ca55_0_coreclk2", R9A09G056_CA55_0_CORE_CLK2, CLK_PLLCA55,
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CDDIV1_DIVCTL2, dtable_1_8),
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DEF_DDIV("ca55_0_coreclk3", R9A09G056_CA55_0_CORE_CLK3, CLK_PLLCA55,
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CDDIV1_DIVCTL3, dtable_1_8),
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DEF_FIXED("iotop_0_shclk", R9A09G056_IOTOP_0_SHCLK, CLK_PLLCM33_DIV16, 1, 1),
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};
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static const struct rzv2h_mod_clk r9a09g056_mod_clks[] __initconst = {
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DEF_MOD_CRITICAL("gic_0_gicclk", CLK_PLLDTY_ACPU_DIV4, 1, 3, 0, 19,
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BUS_MSTOP(3, BIT(5))),
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DEF_MOD("scif_0_clk_pck", CLK_PLLCM33_DIV16, 8, 15, 4, 15,
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BUS_MSTOP(3, BIT(14))),
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DEF_MOD("sdhi_0_imclk", CLK_PLLCLN_DIV8, 10, 3, 5, 3,
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BUS_MSTOP(8, BIT(2))),
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DEF_MOD("sdhi_0_imclk2", CLK_PLLCLN_DIV8, 10, 4, 5, 4,
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BUS_MSTOP(8, BIT(2))),
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DEF_MOD("sdhi_0_clk_hs", CLK_PLLCLN_DIV2, 10, 5, 5, 5,
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BUS_MSTOP(8, BIT(2))),
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DEF_MOD("sdhi_0_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 6, 5, 6,
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BUS_MSTOP(8, BIT(2))),
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DEF_MOD("sdhi_1_imclk", CLK_PLLCLN_DIV8, 10, 7, 5, 7,
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BUS_MSTOP(8, BIT(3))),
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DEF_MOD("sdhi_1_imclk2", CLK_PLLCLN_DIV8, 10, 8, 5, 8,
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BUS_MSTOP(8, BIT(3))),
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DEF_MOD("sdhi_1_clk_hs", CLK_PLLCLN_DIV2, 10, 9, 5, 9,
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BUS_MSTOP(8, BIT(3))),
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DEF_MOD("sdhi_1_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 10, 5, 10,
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BUS_MSTOP(8, BIT(3))),
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DEF_MOD("sdhi_2_imclk", CLK_PLLCLN_DIV8, 10, 11, 5, 11,
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BUS_MSTOP(8, BIT(4))),
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DEF_MOD("sdhi_2_imclk2", CLK_PLLCLN_DIV8, 10, 12, 5, 12,
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BUS_MSTOP(8, BIT(4))),
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DEF_MOD("sdhi_2_clk_hs", CLK_PLLCLN_DIV2, 10, 13, 5, 13,
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BUS_MSTOP(8, BIT(4))),
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DEF_MOD("sdhi_2_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 14, 5, 14,
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BUS_MSTOP(8, BIT(4))),
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};
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static const struct rzv2h_reset r9a09g056_resets[] __initconst = {
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DEF_RST(3, 0, 1, 1), /* SYS_0_PRESETN */
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DEF_RST(3, 8, 1, 9), /* GIC_0_GICRESET_N */
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DEF_RST(3, 9, 1, 10), /* GIC_0_DBG_GICRESET_N */
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DEF_RST(9, 5, 4, 6), /* SCIF_0_RST_SYSTEM_N */
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DEF_RST(10, 7, 4, 24), /* SDHI_0_IXRST */
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DEF_RST(10, 8, 4, 25), /* SDHI_1_IXRST */
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DEF_RST(10, 9, 4, 26), /* SDHI_2_IXRST */
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};
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const struct rzv2h_cpg_info r9a09g056_cpg_info __initconst = {
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/* Core Clocks */
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.core_clks = r9a09g056_core_clks,
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.num_core_clks = ARRAY_SIZE(r9a09g056_core_clks),
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.last_dt_core_clk = LAST_DT_CORE_CLK,
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.num_total_core_clks = MOD_CLK_BASE,
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/* Module Clocks */
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.mod_clks = r9a09g056_mod_clks,
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.num_mod_clks = ARRAY_SIZE(r9a09g056_mod_clks),
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.num_hw_mod_clks = 25 * 16,
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/* Resets */
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.resets = r9a09g056_resets,
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.num_resets = ARRAY_SIZE(r9a09g056_resets),
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.num_mstop_bits = 192,
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};

‎drivers/clk/renesas/rzv2h-cpg.c

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@@ -1020,6 +1020,12 @@ static const struct of_device_id rzv2h_cpg_match[] = {
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.data = &r9a09g047_cpg_info,
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},
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#endif
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#ifdef CONFIG_CLK_R9A09G056
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{
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.compatible = "renesas,r9a09g056-cpg",
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.data = &r9a09g056_cpg_info,
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},
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#endif
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#ifdef CONFIG_CLK_R9A09G057
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{
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.compatible = "renesas,r9a09g057-cpg",

‎drivers/clk/renesas/rzv2h-cpg.h

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@@ -237,6 +237,7 @@ struct rzv2h_cpg_info {
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};
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extern const struct rzv2h_cpg_info r9a09g047_cpg_info;
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extern const struct rzv2h_cpg_info r9a09g056_cpg_info;
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extern const struct rzv2h_cpg_info r9a09g057_cpg_info;
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#endif /* __RENESAS_RZV2H_CPG_H__ */

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