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20 | 20 | .opcode = __opcode, \
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21 | 21 | }
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22 | 22 |
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| 23 | +#define SPI_MEM_DTR_OP_CMD(__opcode, __buswidth) \ |
| 24 | + { \ |
| 25 | + .nbytes = 1, \ |
| 26 | + .opcode = __opcode, \ |
| 27 | + .buswidth = __buswidth, \ |
| 28 | + .dtr = true, \ |
| 29 | + } |
| 30 | + |
23 | 31 | #define SPI_MEM_OP_ADDR(__nbytes, __val, __buswidth) \
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24 | 32 | { \
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25 | 33 | .nbytes = __nbytes, \
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26 | 34 | .buswidth = __buswidth, \
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27 | 35 | .val = __val, \
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28 | 36 | }
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29 | 37 |
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| 38 | +#define SPI_MEM_DTR_OP_ADDR(__nbytes, __val, __buswidth) \ |
| 39 | + { \ |
| 40 | + .nbytes = __nbytes, \ |
| 41 | + .val = __val, \ |
| 42 | + .buswidth = __buswidth, \ |
| 43 | + .dtr = true, \ |
| 44 | + } |
| 45 | + |
30 | 46 | #define SPI_MEM_OP_NO_ADDR { }
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31 | 47 |
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32 | 48 | #define SPI_MEM_OP_DUMMY(__nbytes, __buswidth) \
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35 | 51 | .buswidth = __buswidth, \
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36 | 52 | }
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37 | 53 |
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| 54 | +#define SPI_MEM_DTR_OP_DUMMY(__nbytes, __buswidth) \ |
| 55 | + { \ |
| 56 | + .nbytes = __nbytes, \ |
| 57 | + .buswidth = __buswidth, \ |
| 58 | + .dtr = true, \ |
| 59 | + } |
| 60 | + |
38 | 61 | #define SPI_MEM_OP_NO_DUMMY { }
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39 | 62 |
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40 | 63 | #define SPI_MEM_OP_DATA_IN(__nbytes, __buf, __buswidth) \
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45 | 68 | .buf.in = __buf, \
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46 | 69 | }
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47 | 70 |
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| 71 | +#define SPI_MEM_DTR_OP_DATA_IN(__nbytes, __buf, __buswidth) \ |
| 72 | + { \ |
| 73 | + .dir = SPI_MEM_DATA_IN, \ |
| 74 | + .nbytes = __nbytes, \ |
| 75 | + .buf.in = __buf, \ |
| 76 | + .buswidth = __buswidth, \ |
| 77 | + .dtr = true, \ |
| 78 | + } |
| 79 | + |
48 | 80 | #define SPI_MEM_OP_DATA_OUT(__nbytes, __buf, __buswidth) \
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49 | 81 | { \
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50 | 82 | .buswidth = __buswidth, \
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53 | 85 | .buf.out = __buf, \
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54 | 86 | }
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55 | 87 |
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| 88 | +#define SPI_MEM_DTR_OP_DATA_OUT(__nbytes, __buf, __buswidth) \ |
| 89 | + { \ |
| 90 | + .dir = SPI_MEM_DATA_OUT, \ |
| 91 | + .nbytes = __nbytes, \ |
| 92 | + .buf.out = __buf, \ |
| 93 | + .buswidth = __buswidth, \ |
| 94 | + .dtr = true, \ |
| 95 | + } |
| 96 | + |
56 | 97 | #define SPI_MEM_OP_NO_DATA { }
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57 | 98 |
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58 | 99 | /**
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