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bebarinobebarino
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Merge tag 'sunxi-clk-for-6.13' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-allwinner
Pull Allwinner clk driver updates from Chen-Yu Tsai: - Add sigma-delta modulation settings for audio PLL on the H616 SoC, crucial for accurate audio reproduction - Constify |struct ccu_reset_map| throughout the sunxi-ng clk drivers - Fix the audio PLL divider preset on the D1 SoC - Switch to of_property_present() for checking DT property presence * tag 'sunxi-clk-for-6.13' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: clk: sunxi-ng: Use of_property_present() for non-boolean properties clk: sunxi-ng: d1: Fix PLL_AUDIO0 preset clk: sunxi-ng: Constify struct ccu_reset_map clk: sunxi-ng: h616: Add sigma-delta modulation settings for audio PLL
2 parents 9852d85 + 1054861 commit ea1ba20

26 files changed

+64
-50
lines changed

‎drivers/clk/sunxi-ng/ccu-sun20i-d1-r.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -91,7 +91,7 @@ static struct clk_hw_onecell_data sun20i_d1_r_hw_clks = {
9191
},
9292
};
9393

94-
static struct ccu_reset_map sun20i_d1_r_ccu_resets[] = {
94+
static const struct ccu_reset_map sun20i_d1_r_ccu_resets[] = {
9595
[RST_BUS_R_TIMER] = { 0x11c, BIT(16) },
9696
[RST_BUS_R_TWD] = { 0x12c, BIT(16) },
9797
[RST_BUS_R_PPU] = { 0x1ac, BIT(16) },

‎drivers/clk/sunxi-ng/ccu-sun20i-d1.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1232,7 +1232,7 @@ static struct clk_hw_onecell_data sun20i_d1_hw_clks = {
12321232
},
12331233
};
12341234

1235-
static struct ccu_reset_map sun20i_d1_ccu_resets[] = {
1235+
static const struct ccu_reset_map sun20i_d1_ccu_resets[] = {
12361236
[RST_MBUS] = { 0x540, BIT(30) },
12371237
[RST_BUS_DE] = { 0x60c, BIT(16) },
12381238
[RST_BUS_DI] = { 0x62c, BIT(16) },
@@ -1371,7 +1371,7 @@ static int sun20i_d1_ccu_probe(struct platform_device *pdev)
13711371

13721372
/* Enforce m1 = 0, m0 = 0 for PLL_AUDIO0 */
13731373
val = readl(reg + SUN20I_D1_PLL_AUDIO0_REG);
1374-
val &= ~BIT(1) | BIT(0);
1374+
val &= ~(BIT(1) | BIT(0));
13751375
writel(val, reg + SUN20I_D1_PLL_AUDIO0_REG);
13761376

13771377
/* Force fanout-27M factor N to 0. */

‎drivers/clk/sunxi-ng/ccu-sun4i-a10.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1382,7 +1382,7 @@ static struct clk_hw_onecell_data sun7i_a20_hw_clks = {
13821382
.num = CLK_NUMBER_SUN7I,
13831383
};
13841384

1385-
static struct ccu_reset_map sunxi_a10_a20_ccu_resets[] = {
1385+
static const struct ccu_reset_map sunxi_a10_a20_ccu_resets[] = {
13861386
[RST_USB_PHY0] = { 0x0cc, BIT(0) },
13871387
[RST_USB_PHY1] = { 0x0cc, BIT(1) },
13881388
[RST_USB_PHY2] = { 0x0cc, BIT(2) },

‎drivers/clk/sunxi-ng/ccu-sun50i-a100-r.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -166,7 +166,7 @@ static struct clk_hw_onecell_data sun50i_a100_r_hw_clks = {
166166
.num = CLK_NUMBER,
167167
};
168168

169-
static struct ccu_reset_map sun50i_a100_r_ccu_resets[] = {
169+
static const struct ccu_reset_map sun50i_a100_r_ccu_resets[] = {
170170
[RST_R_APB1_TIMER] = { 0x11c, BIT(16) },
171171
[RST_R_APB1_BUS_PWM] = { 0x13c, BIT(16) },
172172
[RST_R_APB1_PPU] = { 0x17c, BIT(16) },

‎drivers/clk/sunxi-ng/ccu-sun50i-a100.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1061,7 +1061,7 @@ static struct clk_hw_onecell_data sun50i_a100_hw_clks = {
10611061
.num = CLK_NUMBER,
10621062
};
10631063

1064-
static struct ccu_reset_map sun50i_a100_ccu_resets[] = {
1064+
static const struct ccu_reset_map sun50i_a100_ccu_resets[] = {
10651065
[RST_MBUS] = { 0x540, BIT(30) },
10661066

10671067
[RST_BUS_DE] = { 0x60c, BIT(16) },

‎drivers/clk/sunxi-ng/ccu-sun50i-a64.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -858,7 +858,7 @@ static struct clk_hw_onecell_data sun50i_a64_hw_clks = {
858858
.num = CLK_NUMBER,
859859
};
860860

861-
static struct ccu_reset_map sun50i_a64_ccu_resets[] = {
861+
static const struct ccu_reset_map sun50i_a64_ccu_resets[] = {
862862
[RST_USB_PHY0] = { 0x0cc, BIT(0) },
863863
[RST_USB_PHY1] = { 0x0cc, BIT(1) },
864864
[RST_USB_HSIC] = { 0x0cc, BIT(2) },

‎drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -179,7 +179,7 @@ static struct clk_hw_onecell_data sun50i_h616_r_hw_clks = {
179179
.num = CLK_NUMBER,
180180
};
181181

182-
static struct ccu_reset_map sun50i_h6_r_ccu_resets[] = {
182+
static const struct ccu_reset_map sun50i_h6_r_ccu_resets[] = {
183183
[RST_R_APB1_TIMER] = { 0x11c, BIT(16) },
184184
[RST_R_APB1_TWD] = { 0x12c, BIT(16) },
185185
[RST_R_APB1_PWM] = { 0x13c, BIT(16) },
@@ -190,7 +190,7 @@ static struct ccu_reset_map sun50i_h6_r_ccu_resets[] = {
190190
[RST_R_APB1_W1] = { 0x1ec, BIT(16) },
191191
};
192192

193-
static struct ccu_reset_map sun50i_h616_r_ccu_resets[] = {
193+
static const struct ccu_reset_map sun50i_h616_r_ccu_resets[] = {
194194
[RST_R_APB1_TWD] = { 0x12c, BIT(16) },
195195
[RST_R_APB2_I2C] = { 0x19c, BIT(16) },
196196
[RST_R_APB2_RSB] = { 0x1bc, BIT(16) },

‎drivers/clk/sunxi-ng/ccu-sun50i-h6.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1076,7 +1076,7 @@ static struct clk_hw_onecell_data sun50i_h6_hw_clks = {
10761076
.num = CLK_NUMBER,
10771077
};
10781078

1079-
static struct ccu_reset_map sun50i_h6_ccu_resets[] = {
1079+
static const struct ccu_reset_map sun50i_h6_ccu_resets[] = {
10801080
[RST_MBUS] = { 0x540, BIT(30) },
10811081

10821082
[RST_BUS_DE] = { 0x60c, BIT(16) },

‎drivers/clk/sunxi-ng/ccu-sun50i-h616.c

Lines changed: 30 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -216,19 +216,29 @@ static struct ccu_nkmp pll_de_clk = {
216216
};
217217

218218
/*
219-
* TODO: Determine SDM settings for the audio PLL. The manual suggests
220-
* PLL_FACTOR_N=16, PLL_POST_DIV_P=2, OUTPUT_DIV=2, pattern=0xe000c49b
221-
* for 24.576 MHz, and PLL_FACTOR_N=22, PLL_POST_DIV_P=3, OUTPUT_DIV=2,
222-
* pattern=0xe001288c for 22.5792 MHz.
223-
* This clashes with our fixed PLL_POST_DIV_P.
219+
* Sigma-delta modulation settings table obtained from the vendor SDK driver.
220+
* There are additional M0 and M1 divider bits not modelled here, so forced to
221+
* fixed values in the probe routine. Sigma-delta modulation allows providing a
222+
* fractional-N divider in the PLL, to help reaching those specific
223+
* frequencies with less error.
224224
*/
225+
static struct ccu_sdm_setting pll_audio_sdm_table[] = {
226+
{ .rate = 90316800, .pattern = 0xc001288d, .m = 3, .n = 22 },
227+
{ .rate = 98304000, .pattern = 0xc001eb85, .m = 5, .n = 40 },
228+
};
229+
225230
#define SUN50I_H616_PLL_AUDIO_REG 0x078
226231
static struct ccu_nm pll_audio_hs_clk = {
227232
.enable = BIT(31),
228233
.lock = BIT(28),
229234
.n = _SUNXI_CCU_MULT_MIN(8, 8, 12),
230-
.m = _SUNXI_CCU_DIV(1, 1), /* input divider */
235+
.m = _SUNXI_CCU_DIV(16, 6),
236+
.sdm = _SUNXI_CCU_SDM(pll_audio_sdm_table,
237+
BIT(24), 0x178, BIT(31)),
238+
.fixed_post_div = 2,
231239
.common = {
240+
.features = CCU_FEATURE_FIXED_POSTDIV |
241+
CCU_FEATURE_SIGMA_DELTA_MOD,
232242
.reg = 0x078,
233243
.hw.init = CLK_HW_INIT("pll-audio-hs", "osc24M",
234244
&ccu_nm_ops,
@@ -685,18 +695,20 @@ static const struct clk_hw *clk_parent_pll_audio[] = {
685695
};
686696

687697
/*
688-
* The divider of pll-audio is fixed to 24 for now, so 24576000 and 22579200
689-
* rates can be set exactly in conjunction with sigma-delta modulation.
698+
* The PLL_AUDIO_4X clock defaults to 24.5714 MHz according to the manual, with
699+
* a final divider of 1. The 2X and 1X clocks use 2 and 4 respectively. The 1x
700+
* clock is set to either 24576000 or 22579200 for 48Khz and 44.1Khz (and
701+
* multiples).
690702
*/
691703
static CLK_FIXED_FACTOR_HWS(pll_audio_1x_clk, "pll-audio-1x",
692704
clk_parent_pll_audio,
693-
96, 1, CLK_SET_RATE_PARENT);
705+
4, 1, CLK_SET_RATE_PARENT);
694706
static CLK_FIXED_FACTOR_HWS(pll_audio_2x_clk, "pll-audio-2x",
695707
clk_parent_pll_audio,
696-
48, 1, CLK_SET_RATE_PARENT);
708+
2, 1, CLK_SET_RATE_PARENT);
697709
static CLK_FIXED_FACTOR_HWS(pll_audio_4x_clk, "pll-audio-4x",
698710
clk_parent_pll_audio,
699-
24, 1, CLK_SET_RATE_PARENT);
711+
1, 1, CLK_SET_RATE_PARENT);
700712

701713
static const struct clk_hw *pll_periph0_parents[] = {
702714
&pll_periph0_clk.common.hw
@@ -990,7 +1002,7 @@ static struct clk_hw_onecell_data sun50i_h616_hw_clks = {
9901002
.num = CLK_NUMBER,
9911003
};
9921004

993-
static struct ccu_reset_map sun50i_h616_ccu_resets[] = {
1005+
static const struct ccu_reset_map sun50i_h616_ccu_resets[] = {
9941006
[RST_MBUS] = { 0x540, BIT(30) },
9951007

9961008
[RST_BUS_DE] = { 0x60c, BIT(16) },
@@ -1136,12 +1148,14 @@ static int sun50i_h616_ccu_probe(struct platform_device *pdev)
11361148
}
11371149

11381150
/*
1139-
* Force the post-divider of pll-audio to 12 and the output divider
1140-
* of it to 2, so 24576000 and 22579200 rates can be set exactly.
1151+
* Set the output-divider for the pll-audio clocks (M0) to 2 and the
1152+
* input divider (M1) to 1 as recommended by the manual when using
1153+
* SDM.
11411154
*/
11421155
val = readl(reg + SUN50I_H616_PLL_AUDIO_REG);
1143-
val &= ~(GENMASK(21, 16) | BIT(0));
1144-
writel(val | (11 << 16) | BIT(0), reg + SUN50I_H616_PLL_AUDIO_REG);
1156+
val &= ~BIT(1);
1157+
val |= BIT(0);
1158+
writel(val, reg + SUN50I_H616_PLL_AUDIO_REG);
11451159

11461160
/*
11471161
* First clock parent (osc32K) is unusable for CEC. But since there

‎drivers/clk/sunxi-ng/ccu-sun5i.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -731,7 +731,7 @@ static struct clk_hw_onecell_data sun5i_a10s_hw_clks = {
731731
.num = CLK_NUMBER,
732732
};
733733

734-
static struct ccu_reset_map sun5i_a10s_ccu_resets[] = {
734+
static const struct ccu_reset_map sun5i_a10s_ccu_resets[] = {
735735
[RST_USB_PHY0] = { 0x0cc, BIT(0) },
736736
[RST_USB_PHY1] = { 0x0cc, BIT(1) },
737737

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