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Thomas Richterhcahca
Thomas Richter
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s390/cpumf: Update CPU Measurement facility extended counter set support
Update CPU Measurement counter facility support for the extended counter set for machine types 9175 and 9176. Signed-off-by: Thomas Richter <tmricht@linux.ibm.com> Acked-by: Sumanth Korikkar <sumanthk@linux.ibm.com> Signed-off-by: Heiko Carstens <hca@linux.ibm.com>
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-4
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2 files changed

+165
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‎arch/s390/kernel/perf_cpum_cf.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -442,7 +442,7 @@ static void cpum_cf_make_setsize(enum cpumf_ctr_set ctrset)
442442
ctrset_size = 48;
443443
else if (cpumf_ctr_info.csvn >= 3 && cpumf_ctr_info.csvn <= 5)
444444
ctrset_size = 128;
445-
else if (cpumf_ctr_info.csvn == 6 || cpumf_ctr_info.csvn == 7)
445+
else if (cpumf_ctr_info.csvn >= 6 && cpumf_ctr_info.csvn <= 8)
446446
ctrset_size = 160;
447447
break;
448448
case CPUMF_CTR_SET_MT_DIAG:

‎arch/s390/kernel/perf_cpum_cf_events.c

Lines changed: 164 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -237,7 +237,6 @@ CPUMF_EVENT_ATTR(cf_z14, TX_C_TABORT_NO_SPECIAL, 0x00f4);
237237
CPUMF_EVENT_ATTR(cf_z14, TX_C_TABORT_SPECIAL, 0x00f5);
238238
CPUMF_EVENT_ATTR(cf_z14, MT_DIAG_CYCLES_ONE_THR_ACTIVE, 0x01c0);
239239
CPUMF_EVENT_ATTR(cf_z14, MT_DIAG_CYCLES_TWO_THR_ACTIVE, 0x01c1);
240-
241240
CPUMF_EVENT_ATTR(cf_z15, L1D_RO_EXCL_WRITES, 0x0080);
242241
CPUMF_EVENT_ATTR(cf_z15, DTLB2_WRITES, 0x0081);
243242
CPUMF_EVENT_ATTR(cf_z15, DTLB2_MISSES, 0x0082);
@@ -365,6 +364,83 @@ CPUMF_EVENT_ATTR(cf_z16, NNPA_WAIT_LOCK, 0x010d);
365364
CPUMF_EVENT_ATTR(cf_z16, NNPA_HOLD_LOCK, 0x010e);
366365
CPUMF_EVENT_ATTR(cf_z16, MT_DIAG_CYCLES_ONE_THR_ACTIVE, 0x01c0);
367366
CPUMF_EVENT_ATTR(cf_z16, MT_DIAG_CYCLES_TWO_THR_ACTIVE, 0x01c1);
367+
CPUMF_EVENT_ATTR(cf_z17, L1D_RO_EXCL_WRITES, 0x0080);
368+
CPUMF_EVENT_ATTR(cf_z17, DTLB2_WRITES, 0x0081);
369+
CPUMF_EVENT_ATTR(cf_z17, DTLB2_MISSES, 0x0082);
370+
CPUMF_EVENT_ATTR(cf_z17, CRSTE_1MB_WRITES, 0x0083);
371+
CPUMF_EVENT_ATTR(cf_z17, DTLB2_GPAGE_WRITES, 0x0084);
372+
CPUMF_EVENT_ATTR(cf_z17, ITLB2_WRITES, 0x0086);
373+
CPUMF_EVENT_ATTR(cf_z17, ITLB2_MISSES, 0x0087);
374+
CPUMF_EVENT_ATTR(cf_z17, TLB2_PTE_WRITES, 0x0089);
375+
CPUMF_EVENT_ATTR(cf_z17, TLB2_CRSTE_WRITES, 0x008a);
376+
CPUMF_EVENT_ATTR(cf_z17, TLB2_ENGINES_BUSY, 0x008b);
377+
CPUMF_EVENT_ATTR(cf_z17, TX_C_TEND, 0x008c);
378+
CPUMF_EVENT_ATTR(cf_z17, TX_NC_TEND, 0x008d);
379+
CPUMF_EVENT_ATTR(cf_z17, L1C_TLB2_MISSES, 0x008f);
380+
CPUMF_EVENT_ATTR(cf_z17, DCW_REQ, 0x0091);
381+
CPUMF_EVENT_ATTR(cf_z17, DCW_REQ_IV, 0x0092);
382+
CPUMF_EVENT_ATTR(cf_z17, DCW_REQ_CHIP_HIT, 0x0093);
383+
CPUMF_EVENT_ATTR(cf_z17, DCW_REQ_DRAWER_HIT, 0x0094);
384+
CPUMF_EVENT_ATTR(cf_z17, DCW_ON_CHIP, 0x0095);
385+
CPUMF_EVENT_ATTR(cf_z17, DCW_ON_CHIP_IV, 0x0096);
386+
CPUMF_EVENT_ATTR(cf_z17, DCW_ON_CHIP_CHIP_HIT, 0x0097);
387+
CPUMF_EVENT_ATTR(cf_z17, DCW_ON_CHIP_DRAWER_HIT, 0x0098);
388+
CPUMF_EVENT_ATTR(cf_z17, DCW_ON_MODULE, 0x0099);
389+
CPUMF_EVENT_ATTR(cf_z17, DCW_ON_DRAWER, 0x009a);
390+
CPUMF_EVENT_ATTR(cf_z17, DCW_OFF_DRAWER, 0x009b);
391+
CPUMF_EVENT_ATTR(cf_z17, DCW_ON_CHIP_MEMORY, 0x009c);
392+
CPUMF_EVENT_ATTR(cf_z17, DCW_ON_MODULE_MEMORY, 0x009d);
393+
CPUMF_EVENT_ATTR(cf_z17, DCW_ON_DRAWER_MEMORY, 0x009e);
394+
CPUMF_EVENT_ATTR(cf_z17, DCW_OFF_DRAWER_MEMORY, 0x009f);
395+
CPUMF_EVENT_ATTR(cf_z17, IDCW_ON_MODULE_IV, 0x00a0);
396+
CPUMF_EVENT_ATTR(cf_z17, IDCW_ON_MODULE_CHIP_HIT, 0x00a1);
397+
CPUMF_EVENT_ATTR(cf_z17, IDCW_ON_MODULE_DRAWER_HIT, 0x00a2);
398+
CPUMF_EVENT_ATTR(cf_z17, IDCW_ON_DRAWER_IV, 0x00a3);
399+
CPUMF_EVENT_ATTR(cf_z17, IDCW_ON_DRAWER_CHIP_HIT, 0x00a4);
400+
CPUMF_EVENT_ATTR(cf_z17, IDCW_ON_DRAWER_DRAWER_HIT, 0x00a5);
401+
CPUMF_EVENT_ATTR(cf_z17, IDCW_OFF_DRAWER_IV, 0x00a6);
402+
CPUMF_EVENT_ATTR(cf_z17, IDCW_OFF_DRAWER_CHIP_HIT, 0x00a7);
403+
CPUMF_EVENT_ATTR(cf_z17, IDCW_OFF_DRAWER_DRAWER_HIT, 0x00a8);
404+
CPUMF_EVENT_ATTR(cf_z17, ICW_REQ, 0x00a9);
405+
CPUMF_EVENT_ATTR(cf_z17, ICW_REQ_IV, 0x00aa);
406+
CPUMF_EVENT_ATTR(cf_z17, ICW_REQ_CHIP_HIT, 0x00ab);
407+
CPUMF_EVENT_ATTR(cf_z17, ICW_REQ_DRAWER_HIT, 0x00ac);
408+
CPUMF_EVENT_ATTR(cf_z17, ICW_ON_CHIP, 0x00ad);
409+
CPUMF_EVENT_ATTR(cf_z17, ICW_ON_CHIP_IV, 0x00ae);
410+
CPUMF_EVENT_ATTR(cf_z17, ICW_ON_CHIP_CHIP_HIT, 0x00af);
411+
CPUMF_EVENT_ATTR(cf_z17, ICW_ON_CHIP_DRAWER_HIT, 0x00b0);
412+
CPUMF_EVENT_ATTR(cf_z17, ICW_ON_MODULE, 0x00b1);
413+
CPUMF_EVENT_ATTR(cf_z17, ICW_ON_DRAWER, 0x00b2);
414+
CPUMF_EVENT_ATTR(cf_z17, ICW_OFF_DRAWER, 0x00b3);
415+
CPUMF_EVENT_ATTR(cf_z17, CYCLES_SAMETHRD, 0x00ca);
416+
CPUMF_EVENT_ATTR(cf_z17, CYCLES_DIFFTHRD, 0x00cb);
417+
CPUMF_EVENT_ATTR(cf_z17, INST_SAMETHRD, 0x00cc);
418+
CPUMF_EVENT_ATTR(cf_z17, INST_DIFFTHRD, 0x00cd);
419+
CPUMF_EVENT_ATTR(cf_z17, WRONG_BRANCH_PREDICTION, 0x00ce);
420+
CPUMF_EVENT_ATTR(cf_z17, VX_BCD_EXECUTION_SLOTS, 0x00e1);
421+
CPUMF_EVENT_ATTR(cf_z17, DECIMAL_INSTRUCTIONS, 0x00e2);
422+
CPUMF_EVENT_ATTR(cf_z17, LAST_HOST_TRANSLATIONS, 0x00e8);
423+
CPUMF_EVENT_ATTR(cf_z17, TX_NC_TABORT, 0x00f4);
424+
CPUMF_EVENT_ATTR(cf_z17, TX_C_TABORT_NO_SPECIAL, 0x00f5);
425+
CPUMF_EVENT_ATTR(cf_z17, TX_C_TABORT_SPECIAL, 0x00f6);
426+
CPUMF_EVENT_ATTR(cf_z17, DFLT_ACCESS, 0x00f8);
427+
CPUMF_EVENT_ATTR(cf_z17, DFLT_CYCLES, 0x00fd);
428+
CPUMF_EVENT_ATTR(cf_z17, SORTL, 0x0100);
429+
CPUMF_EVENT_ATTR(cf_z17, DFLT_CC, 0x0109);
430+
CPUMF_EVENT_ATTR(cf_z17, DFLT_CCFINISH, 0x010a);
431+
CPUMF_EVENT_ATTR(cf_z17, NNPA_INVOCATIONS, 0x010b);
432+
CPUMF_EVENT_ATTR(cf_z17, NNPA_COMPLETIONS, 0x010c);
433+
CPUMF_EVENT_ATTR(cf_z17, NNPA_WAIT_LOCK, 0x010d);
434+
CPUMF_EVENT_ATTR(cf_z17, NNPA_HOLD_LOCK, 0x010e);
435+
CPUMF_EVENT_ATTR(cf_z17, NNPA_INST_ONCHIP, 0x0110);
436+
CPUMF_EVENT_ATTR(cf_z17, NNPA_INST_OFFCHIP, 0x0111);
437+
CPUMF_EVENT_ATTR(cf_z17, NNPA_INST_DIFF, 0x0112);
438+
CPUMF_EVENT_ATTR(cf_z17, NNPA_4K_PREFETCH, 0x0114);
439+
CPUMF_EVENT_ATTR(cf_z17, NNPA_COMPL_LOCK, 0x0115);
440+
CPUMF_EVENT_ATTR(cf_z17, NNPA_RETRY_LOCK, 0x0116);
441+
CPUMF_EVENT_ATTR(cf_z17, NNPA_RETRY_LOCK_WITH_PLO, 0x0117);
442+
CPUMF_EVENT_ATTR(cf_z17, MT_DIAG_CYCLES_ONE_THR_ACTIVE, 0x01c0);
443+
CPUMF_EVENT_ATTR(cf_z17, MT_DIAG_CYCLES_TWO_THR_ACTIVE, 0x01c1);
368444

369445
static struct attribute *cpumcf_fvn1_pmu_event_attr[] __initdata = {
370446
CPUMF_EVENT_PTR(cf_fvn1, CPU_CYCLES),
@@ -414,7 +490,7 @@ static struct attribute *cpumcf_svn_12345_pmu_event_attr[] __initdata = {
414490
NULL,
415491
};
416492

417-
static struct attribute *cpumcf_svn_67_pmu_event_attr[] __initdata = {
493+
static struct attribute *cpumcf_svn_678_pmu_event_attr[] __initdata = {
418494
CPUMF_EVENT_PTR(cf_svn_12345, PRNG_FUNCTIONS),
419495
CPUMF_EVENT_PTR(cf_svn_12345, PRNG_CYCLES),
420496
CPUMF_EVENT_PTR(cf_svn_12345, PRNG_BLOCKED_FUNCTIONS),
@@ -779,6 +855,87 @@ static struct attribute *cpumcf_z16_pmu_event_attr[] __initdata = {
779855
NULL,
780856
};
781857

858+
static struct attribute *cpumcf_z17_pmu_event_attr[] __initdata = {
859+
CPUMF_EVENT_PTR(cf_z17, L1D_RO_EXCL_WRITES),
860+
CPUMF_EVENT_PTR(cf_z17, DTLB2_WRITES),
861+
CPUMF_EVENT_PTR(cf_z17, DTLB2_MISSES),
862+
CPUMF_EVENT_PTR(cf_z17, CRSTE_1MB_WRITES),
863+
CPUMF_EVENT_PTR(cf_z17, DTLB2_GPAGE_WRITES),
864+
CPUMF_EVENT_PTR(cf_z17, ITLB2_WRITES),
865+
CPUMF_EVENT_PTR(cf_z17, ITLB2_MISSES),
866+
CPUMF_EVENT_PTR(cf_z17, TLB2_PTE_WRITES),
867+
CPUMF_EVENT_PTR(cf_z17, TLB2_CRSTE_WRITES),
868+
CPUMF_EVENT_PTR(cf_z17, TLB2_ENGINES_BUSY),
869+
CPUMF_EVENT_PTR(cf_z17, TX_C_TEND),
870+
CPUMF_EVENT_PTR(cf_z17, TX_NC_TEND),
871+
CPUMF_EVENT_PTR(cf_z17, L1C_TLB2_MISSES),
872+
CPUMF_EVENT_PTR(cf_z17, DCW_REQ),
873+
CPUMF_EVENT_PTR(cf_z17, DCW_REQ_IV),
874+
CPUMF_EVENT_PTR(cf_z17, DCW_REQ_CHIP_HIT),
875+
CPUMF_EVENT_PTR(cf_z17, DCW_REQ_DRAWER_HIT),
876+
CPUMF_EVENT_PTR(cf_z17, DCW_ON_CHIP),
877+
CPUMF_EVENT_PTR(cf_z17, DCW_ON_CHIP_IV),
878+
CPUMF_EVENT_PTR(cf_z17, DCW_ON_CHIP_CHIP_HIT),
879+
CPUMF_EVENT_PTR(cf_z17, DCW_ON_CHIP_DRAWER_HIT),
880+
CPUMF_EVENT_PTR(cf_z17, DCW_ON_MODULE),
881+
CPUMF_EVENT_PTR(cf_z17, DCW_ON_DRAWER),
882+
CPUMF_EVENT_PTR(cf_z17, DCW_OFF_DRAWER),
883+
CPUMF_EVENT_PTR(cf_z17, DCW_ON_CHIP_MEMORY),
884+
CPUMF_EVENT_PTR(cf_z17, DCW_ON_MODULE_MEMORY),
885+
CPUMF_EVENT_PTR(cf_z17, DCW_ON_DRAWER_MEMORY),
886+
CPUMF_EVENT_PTR(cf_z17, DCW_OFF_DRAWER_MEMORY),
887+
CPUMF_EVENT_PTR(cf_z17, IDCW_ON_MODULE_IV),
888+
CPUMF_EVENT_PTR(cf_z17, IDCW_ON_MODULE_CHIP_HIT),
889+
CPUMF_EVENT_PTR(cf_z17, IDCW_ON_MODULE_DRAWER_HIT),
890+
CPUMF_EVENT_PTR(cf_z17, IDCW_ON_DRAWER_IV),
891+
CPUMF_EVENT_PTR(cf_z17, IDCW_ON_DRAWER_CHIP_HIT),
892+
CPUMF_EVENT_PTR(cf_z17, IDCW_ON_DRAWER_DRAWER_HIT),
893+
CPUMF_EVENT_PTR(cf_z17, IDCW_OFF_DRAWER_IV),
894+
CPUMF_EVENT_PTR(cf_z17, IDCW_OFF_DRAWER_CHIP_HIT),
895+
CPUMF_EVENT_PTR(cf_z17, IDCW_OFF_DRAWER_DRAWER_HIT),
896+
CPUMF_EVENT_PTR(cf_z17, ICW_REQ),
897+
CPUMF_EVENT_PTR(cf_z17, ICW_REQ_IV),
898+
CPUMF_EVENT_PTR(cf_z17, ICW_REQ_CHIP_HIT),
899+
CPUMF_EVENT_PTR(cf_z17, ICW_REQ_DRAWER_HIT),
900+
CPUMF_EVENT_PTR(cf_z17, ICW_ON_CHIP),
901+
CPUMF_EVENT_PTR(cf_z17, ICW_ON_CHIP_IV),
902+
CPUMF_EVENT_PTR(cf_z17, ICW_ON_CHIP_CHIP_HIT),
903+
CPUMF_EVENT_PTR(cf_z17, ICW_ON_CHIP_DRAWER_HIT),
904+
CPUMF_EVENT_PTR(cf_z17, ICW_ON_MODULE),
905+
CPUMF_EVENT_PTR(cf_z17, ICW_ON_DRAWER),
906+
CPUMF_EVENT_PTR(cf_z17, ICW_OFF_DRAWER),
907+
CPUMF_EVENT_PTR(cf_z17, CYCLES_SAMETHRD),
908+
CPUMF_EVENT_PTR(cf_z17, CYCLES_DIFFTHRD),
909+
CPUMF_EVENT_PTR(cf_z17, INST_SAMETHRD),
910+
CPUMF_EVENT_PTR(cf_z17, INST_DIFFTHRD),
911+
CPUMF_EVENT_PTR(cf_z17, WRONG_BRANCH_PREDICTION),
912+
CPUMF_EVENT_PTR(cf_z17, VX_BCD_EXECUTION_SLOTS),
913+
CPUMF_EVENT_PTR(cf_z17, DECIMAL_INSTRUCTIONS),
914+
CPUMF_EVENT_PTR(cf_z17, LAST_HOST_TRANSLATIONS),
915+
CPUMF_EVENT_PTR(cf_z17, TX_NC_TABORT),
916+
CPUMF_EVENT_PTR(cf_z17, TX_C_TABORT_NO_SPECIAL),
917+
CPUMF_EVENT_PTR(cf_z17, TX_C_TABORT_SPECIAL),
918+
CPUMF_EVENT_PTR(cf_z17, DFLT_ACCESS),
919+
CPUMF_EVENT_PTR(cf_z17, DFLT_CYCLES),
920+
CPUMF_EVENT_PTR(cf_z17, SORTL),
921+
CPUMF_EVENT_PTR(cf_z17, DFLT_CC),
922+
CPUMF_EVENT_PTR(cf_z17, DFLT_CCFINISH),
923+
CPUMF_EVENT_PTR(cf_z17, NNPA_INVOCATIONS),
924+
CPUMF_EVENT_PTR(cf_z17, NNPA_COMPLETIONS),
925+
CPUMF_EVENT_PTR(cf_z17, NNPA_WAIT_LOCK),
926+
CPUMF_EVENT_PTR(cf_z17, NNPA_HOLD_LOCK),
927+
CPUMF_EVENT_PTR(cf_z17, NNPA_INST_ONCHIP),
928+
CPUMF_EVENT_PTR(cf_z17, NNPA_INST_OFFCHIP),
929+
CPUMF_EVENT_PTR(cf_z17, NNPA_INST_DIFF),
930+
CPUMF_EVENT_PTR(cf_z17, NNPA_4K_PREFETCH),
931+
CPUMF_EVENT_PTR(cf_z17, NNPA_COMPL_LOCK),
932+
CPUMF_EVENT_PTR(cf_z17, NNPA_RETRY_LOCK),
933+
CPUMF_EVENT_PTR(cf_z17, NNPA_RETRY_LOCK_WITH_PLO),
934+
CPUMF_EVENT_PTR(cf_z17, MT_DIAG_CYCLES_ONE_THR_ACTIVE),
935+
CPUMF_EVENT_PTR(cf_z17, MT_DIAG_CYCLES_TWO_THR_ACTIVE),
936+
NULL,
937+
};
938+
782939
/* END: CPUM_CF COUNTER DEFINITIONS ===================================== */
783940

784941
static struct attribute_group cpumcf_pmu_events_group = {
@@ -859,7 +1016,7 @@ __init const struct attribute_group **cpumf_cf_event_group(void)
8591016
if (ci.csvn >= 1 && ci.csvn <= 5)
8601017
csvn = cpumcf_svn_12345_pmu_event_attr;
8611018
else if (ci.csvn >= 6)
862-
csvn = cpumcf_svn_67_pmu_event_attr;
1019+
csvn = cpumcf_svn_678_pmu_event_attr;
8631020

8641021
/* Determine model-specific counter set(s) */
8651022
get_cpu_id(&cpu_id);
@@ -892,6 +1049,10 @@ __init const struct attribute_group **cpumf_cf_event_group(void)
8921049
case 0x3932:
8931050
model = cpumcf_z16_pmu_event_attr;
8941051
break;
1052+
case 0x9175:
1053+
case 0x9176:
1054+
model = cpumcf_z17_pmu_event_attr;
1055+
break;
8951056
default:
8961057
model = none;
8971058
break;

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