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clk: qcom: gcc-sm8550: Don't use parking clk_ops for QUPs
The QUPs aren't shared in a way that requires parking the RCG at an always on parent in case some other entity turns on the clk. The hardware is capable of setting a new frequency itself with the DFS mode, so parking is unnecessary. Furthermore, there aren't any GDSCs for these devices, so there isn't a possibility of the GDSC turning on the clks for housekeeping purposes. This wasn't a problem to mark these clks shared until we started parking shared RCGs at clk registration time in commit 01a0a6c ("clk: qcom: Park shared RCGs upon registration"). Parking at init is actually harmful to the UART when earlycon is used. If the device is pumping out data while the frequency changes you'll see garbage on the serial console until the driver can probe and actually set a proper frequency. Revert the QUP part of commit 929c75d ("clk: qcom: gcc-sm8550: Mark RCGs shared where applicable") so that the QUPs don't get parked during clk registration and break UART operations. Fixes: 01a0a6c ("clk: qcom: Park shared RCGs upon registration") Fixes: 929c75d ("clk: qcom: gcc-sm8550: Mark RCGs shared where applicable") Cc: Konrad Dybcio <konradybcio@kernel.org> Cc: Bjorn Andersson <andersson@kernel.org> Cc: Taniya Das <quic_tdas@quicinc.com> Reported-by: Amit Pundir <amit.pundir@linaro.org> Closes: https://lore.kernel.org/CAMi1Hd1KQBE4kKUdAn8E5FV+BiKzuv+8FoyWQrrTHPDoYTuhgA@mail.gmail.com Signed-off-by: Stephen Boyd <swboyd@chromium.org> Link: https://lore.kernel.org/r/20240819233628.2074654-2-swboyd@chromium.org Tested-by: Amit Pundir <amit.pundir@linaro.org> Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-QRD Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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drivers/clk/qcom/gcc-sm8550.c

Lines changed: 26 additions & 26 deletions
Original file line numberDiff line numberDiff line change
@@ -536,7 +536,7 @@ static struct clk_rcg2 gcc_qupv3_i2c_s0_clk_src = {
536536
.parent_data = gcc_parent_data_0,
537537
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
538538
.flags = CLK_SET_RATE_PARENT,
539-
.ops = &clk_rcg2_shared_ops,
539+
.ops = &clk_rcg2_ops,
540540
},
541541
};
542542

@@ -551,7 +551,7 @@ static struct clk_rcg2 gcc_qupv3_i2c_s1_clk_src = {
551551
.parent_data = gcc_parent_data_0,
552552
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
553553
.flags = CLK_SET_RATE_PARENT,
554-
.ops = &clk_rcg2_shared_ops,
554+
.ops = &clk_rcg2_ops,
555555
},
556556
};
557557

@@ -566,7 +566,7 @@ static struct clk_rcg2 gcc_qupv3_i2c_s2_clk_src = {
566566
.parent_data = gcc_parent_data_0,
567567
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
568568
.flags = CLK_SET_RATE_PARENT,
569-
.ops = &clk_rcg2_shared_ops,
569+
.ops = &clk_rcg2_ops,
570570
},
571571
};
572572

@@ -581,7 +581,7 @@ static struct clk_rcg2 gcc_qupv3_i2c_s3_clk_src = {
581581
.parent_data = gcc_parent_data_0,
582582
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
583583
.flags = CLK_SET_RATE_PARENT,
584-
.ops = &clk_rcg2_shared_ops,
584+
.ops = &clk_rcg2_ops,
585585
},
586586
};
587587

@@ -596,7 +596,7 @@ static struct clk_rcg2 gcc_qupv3_i2c_s4_clk_src = {
596596
.parent_data = gcc_parent_data_0,
597597
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
598598
.flags = CLK_SET_RATE_PARENT,
599-
.ops = &clk_rcg2_shared_ops,
599+
.ops = &clk_rcg2_ops,
600600
},
601601
};
602602

@@ -611,7 +611,7 @@ static struct clk_rcg2 gcc_qupv3_i2c_s5_clk_src = {
611611
.parent_data = gcc_parent_data_0,
612612
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
613613
.flags = CLK_SET_RATE_PARENT,
614-
.ops = &clk_rcg2_shared_ops,
614+
.ops = &clk_rcg2_ops,
615615
},
616616
};
617617

@@ -626,7 +626,7 @@ static struct clk_rcg2 gcc_qupv3_i2c_s6_clk_src = {
626626
.parent_data = gcc_parent_data_0,
627627
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
628628
.flags = CLK_SET_RATE_PARENT,
629-
.ops = &clk_rcg2_shared_ops,
629+
.ops = &clk_rcg2_ops,
630630
},
631631
};
632632

@@ -641,7 +641,7 @@ static struct clk_rcg2 gcc_qupv3_i2c_s7_clk_src = {
641641
.parent_data = gcc_parent_data_0,
642642
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
643643
.flags = CLK_SET_RATE_PARENT,
644-
.ops = &clk_rcg2_shared_ops,
644+
.ops = &clk_rcg2_ops,
645645
},
646646
};
647647

@@ -656,7 +656,7 @@ static struct clk_rcg2 gcc_qupv3_i2c_s8_clk_src = {
656656
.parent_data = gcc_parent_data_0,
657657
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
658658
.flags = CLK_SET_RATE_PARENT,
659-
.ops = &clk_rcg2_shared_ops,
659+
.ops = &clk_rcg2_ops,
660660
},
661661
};
662662

@@ -671,7 +671,7 @@ static struct clk_rcg2 gcc_qupv3_i2c_s9_clk_src = {
671671
.parent_data = gcc_parent_data_0,
672672
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
673673
.flags = CLK_SET_RATE_PARENT,
674-
.ops = &clk_rcg2_shared_ops,
674+
.ops = &clk_rcg2_ops,
675675
},
676676
};
677677

@@ -700,7 +700,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = {
700700
.parent_data = gcc_parent_data_0,
701701
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
702702
.flags = CLK_SET_RATE_PARENT,
703-
.ops = &clk_rcg2_shared_ops,
703+
.ops = &clk_rcg2_ops,
704704
};
705705

706706
static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {
@@ -717,7 +717,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = {
717717
.parent_data = gcc_parent_data_0,
718718
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
719719
.flags = CLK_SET_RATE_PARENT,
720-
.ops = &clk_rcg2_shared_ops,
720+
.ops = &clk_rcg2_ops,
721721
};
722722

723723
static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = {
@@ -750,7 +750,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = {
750750
.parent_data = gcc_parent_data_0,
751751
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
752752
.flags = CLK_SET_RATE_PARENT,
753-
.ops = &clk_rcg2_shared_ops,
753+
.ops = &clk_rcg2_ops,
754754
};
755755

756756
static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = {
@@ -767,7 +767,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = {
767767
.parent_data = gcc_parent_data_0,
768768
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
769769
.flags = CLK_SET_RATE_PARENT,
770-
.ops = &clk_rcg2_shared_ops,
770+
.ops = &clk_rcg2_ops,
771771
};
772772

773773
static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = {
@@ -784,7 +784,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = {
784784
.parent_data = gcc_parent_data_0,
785785
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
786786
.flags = CLK_SET_RATE_PARENT,
787-
.ops = &clk_rcg2_shared_ops,
787+
.ops = &clk_rcg2_ops,
788788
};
789789

790790
static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = {
@@ -801,7 +801,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = {
801801
.parent_data = gcc_parent_data_0,
802802
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
803803
.flags = CLK_SET_RATE_PARENT,
804-
.ops = &clk_rcg2_shared_ops,
804+
.ops = &clk_rcg2_ops,
805805
};
806806

807807
static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = {
@@ -818,7 +818,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s6_clk_src_init = {
818818
.parent_data = gcc_parent_data_0,
819819
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
820820
.flags = CLK_SET_RATE_PARENT,
821-
.ops = &clk_rcg2_shared_ops,
821+
.ops = &clk_rcg2_ops,
822822
};
823823

824824
static struct clk_rcg2 gcc_qupv3_wrap1_s6_clk_src = {
@@ -835,7 +835,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s7_clk_src_init = {
835835
.parent_data = gcc_parent_data_0,
836836
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
837837
.flags = CLK_SET_RATE_PARENT,
838-
.ops = &clk_rcg2_shared_ops,
838+
.ops = &clk_rcg2_ops,
839839
};
840840

841841
static struct clk_rcg2 gcc_qupv3_wrap1_s7_clk_src = {
@@ -852,7 +852,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s0_clk_src_init = {
852852
.parent_data = gcc_parent_data_0,
853853
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
854854
.flags = CLK_SET_RATE_PARENT,
855-
.ops = &clk_rcg2_shared_ops,
855+
.ops = &clk_rcg2_ops,
856856
};
857857

858858
static struct clk_rcg2 gcc_qupv3_wrap2_s0_clk_src = {
@@ -869,7 +869,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s1_clk_src_init = {
869869
.parent_data = gcc_parent_data_0,
870870
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
871871
.flags = CLK_SET_RATE_PARENT,
872-
.ops = &clk_rcg2_shared_ops,
872+
.ops = &clk_rcg2_ops,
873873
};
874874

875875
static struct clk_rcg2 gcc_qupv3_wrap2_s1_clk_src = {
@@ -886,7 +886,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s2_clk_src_init = {
886886
.parent_data = gcc_parent_data_0,
887887
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
888888
.flags = CLK_SET_RATE_PARENT,
889-
.ops = &clk_rcg2_shared_ops,
889+
.ops = &clk_rcg2_ops,
890890
};
891891

892892
static struct clk_rcg2 gcc_qupv3_wrap2_s2_clk_src = {
@@ -903,7 +903,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s3_clk_src_init = {
903903
.parent_data = gcc_parent_data_0,
904904
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
905905
.flags = CLK_SET_RATE_PARENT,
906-
.ops = &clk_rcg2_shared_ops,
906+
.ops = &clk_rcg2_ops,
907907
};
908908

909909
static struct clk_rcg2 gcc_qupv3_wrap2_s3_clk_src = {
@@ -920,7 +920,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s4_clk_src_init = {
920920
.parent_data = gcc_parent_data_0,
921921
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
922922
.flags = CLK_SET_RATE_PARENT,
923-
.ops = &clk_rcg2_shared_ops,
923+
.ops = &clk_rcg2_ops,
924924
};
925925

926926
static struct clk_rcg2 gcc_qupv3_wrap2_s4_clk_src = {
@@ -937,7 +937,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s5_clk_src_init = {
937937
.parent_data = gcc_parent_data_0,
938938
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
939939
.flags = CLK_SET_RATE_PARENT,
940-
.ops = &clk_rcg2_shared_ops,
940+
.ops = &clk_rcg2_ops,
941941
};
942942

943943
static struct clk_rcg2 gcc_qupv3_wrap2_s5_clk_src = {
@@ -975,7 +975,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s6_clk_src_init = {
975975
.parent_data = gcc_parent_data_8,
976976
.num_parents = ARRAY_SIZE(gcc_parent_data_8),
977977
.flags = CLK_SET_RATE_PARENT,
978-
.ops = &clk_rcg2_shared_ops,
978+
.ops = &clk_rcg2_ops,
979979
};
980980

981981
static struct clk_rcg2 gcc_qupv3_wrap2_s6_clk_src = {
@@ -992,7 +992,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s7_clk_src_init = {
992992
.parent_data = gcc_parent_data_0,
993993
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
994994
.flags = CLK_SET_RATE_PARENT,
995-
.ops = &clk_rcg2_shared_ops,
995+
.ops = &clk_rcg2_ops,
996996
};
997997

998998
static struct clk_rcg2 gcc_qupv3_wrap2_s7_clk_src = {

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