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Gregory Pricedavejiang
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cxl: core/region - ignore interleave granularity when ways=1
When validating decoder IW/IG when setting up regions, the granularity is irrelevant when iw=1 - all accesses will always route to the only target anyway - so all ig values are "correct". Loosen the requirement that `ig = (parent_iw * parent_ig)` when iw=1. On some Zen5 platforms, the platform BIOS specifies a 256-byte interleave granularity window for host bridges when there is only one target downstream. This leads to Linux rejecting the configuration of a region with a x2 root with two x1 hostbridges. Decoder Programming: root - iw:2 ig:256 hb1 - iw:1 ig:256 (Linux expects 512) hb2 - iw:1 ig:256 (Linux expects 512) ep1 - iw:2 ig:256 ep2 - iw:2 ig:256 This change allows all decoders downstream of a passthrough decoder to also be configured as passthrough (iw:1 ig:X), but still disallows downstream decoders from applying subsequent interleaves. e.g. in the above example if there was another decoder south of hb1 attempting to interleave 2 endpoints - Linux would enforce hb1.ig=512 because the southern decoder would have iw:2 and require ig=pig*piw. [DJ: Fixed up against 6.15-rc1] Signed-off-by: Gregory Price <gourry@gourry.net> Reviewed-by: Dave Jiang <dave.jiang@intel.com> Tested-by: Li Zhijian <lizhijian@fujitsu.com> Reviewed-by: Davidlohr Bueso <dave@stgolabs.net> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Reviewed-by: Dan Williams <dan.j.williams@intel.com> Link: https://patch.msgid.link/20250402232552.999634-1-gourry@gourry.net Signed-off-by: Dave Jiang <dave.jiang@intel.com>
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drivers/cxl/core/region.c

Lines changed: 1 addition & 1 deletion
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@@ -1446,7 +1446,7 @@ static int cxl_port_setup_targets(struct cxl_port *port,
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if (test_bit(CXL_REGION_F_AUTO, &cxlr->flags)) {
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if (cxld->interleave_ways != iw ||
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cxld->interleave_granularity != ig ||
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(iw > 1 && cxld->interleave_granularity != ig) ||
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!region_res_match_cxl_range(p, &cxld->hpa_range) ||
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((cxld->flags & CXL_DECODER_F_ENABLE) == 0)) {
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dev_err(&cxlr->dev,

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