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clk: renesas: rzv2h: Add support for static mux clocks
Add support for `CLK_TYPE_SMUX` to register static muxed clocks on the Renesas RZ/V2H(P) SoC. Extend `cpg_core_clk` to include parent names, mux flags, and a new `smuxed` struct. Update clock registration to handle static mux clocks. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250407165202.197570-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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drivers/clk/renesas/rzv2h-cpg.c

Lines changed: 21 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -393,6 +393,24 @@ rzv2h_cpg_ddiv_clk_register(const struct cpg_core_clk *core,
393393
return div->hw.clk;
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}
395395

396+
static struct clk * __init
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rzv2h_cpg_mux_clk_register(const struct cpg_core_clk *core,
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struct rzv2h_cpg_priv *priv)
399+
{
400+
struct smuxed mux = core->cfg.smux;
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const struct clk_hw *clk_hw;
402+
403+
clk_hw = devm_clk_hw_register_mux(priv->dev, core->name,
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core->parent_names, core->num_parents,
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core->flag, priv->base + mux.offset,
406+
mux.shift, mux.width,
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core->mux_flags, &priv->rmw_lock);
408+
if (IS_ERR(clk_hw))
409+
return ERR_CAST(clk_hw);
410+
411+
return clk_hw->clk;
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}
413+
396414
static struct clk
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*rzv2h_cpg_clk_src_twocell_get(struct of_phandle_args *clkspec,
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void *data)
@@ -477,6 +495,9 @@ rzv2h_cpg_register_core_clk(const struct cpg_core_clk *core,
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case CLK_TYPE_DDIV:
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clk = rzv2h_cpg_ddiv_clk_register(core, priv);
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break;
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case CLK_TYPE_SMUX:
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clk = rzv2h_cpg_mux_clk_register(core, priv);
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break;
480501
default:
481502
goto fail;
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}

drivers/clk/renesas/rzv2h-cpg.h

Lines changed: 32 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -53,6 +53,26 @@ struct ddiv {
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.monbit = _monbit \
5454
})
5555

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/**
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* struct smuxed - Structure for static muxed clocks
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*
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* @offset: register offset
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* @shift: position of the divider field
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* @width: width of the divider field
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*/
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struct smuxed {
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unsigned int offset:11;
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unsigned int shift:4;
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unsigned int width:4;
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};
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#define SMUX_PACK(_offset, _shift, _width) \
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((struct smuxed){ \
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.offset = (_offset), \
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.shift = (_shift), \
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.width = (_width), \
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})
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5676
#define CPG_CDDIV0 (0x400)
5777
#define CPG_CDDIV1 (0x404)
5878
#define CPG_CDDIV3 (0x40C)
@@ -96,8 +116,12 @@ struct cpg_core_clk {
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unsigned int conf;
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struct ddiv ddiv;
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struct pll pll;
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struct smuxed smux;
99120
} cfg;
100121
const struct clk_div_table *dtable;
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const char * const *parent_names;
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unsigned int num_parents;
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u8 mux_flags;
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u32 flag;
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};
103127

@@ -107,6 +131,7 @@ enum clk_types {
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CLK_TYPE_FF, /* Fixed Factor Clock */
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CLK_TYPE_PLL,
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CLK_TYPE_DDIV, /* Dynamic Switching Divider */
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CLK_TYPE_SMUX, /* Static Mux */
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};
111136

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#define DEF_TYPE(_name, _id, _type...) \
@@ -125,6 +150,13 @@ enum clk_types {
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.parent = _parent, \
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.dtable = _dtable, \
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.flag = CLK_DIVIDER_HIWORD_MASK)
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#define DEF_SMUX(_name, _id, _smux_packed, _parent_names) \
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DEF_TYPE(_name, _id, CLK_TYPE_SMUX, \
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.cfg.smux = _smux_packed, \
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.parent_names = _parent_names, \
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.num_parents = ARRAY_SIZE(_parent_names), \
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.flag = CLK_SET_RATE_PARENT, \
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.mux_flags = CLK_MUX_HIWORD_MASK)
128160

129161
/**
130162
* struct rzv2h_mod_clk - Module Clocks definitions

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