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bebarinobebarino
committed
Merge tag 'qcom-clk-for-6.16' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into clk-qcom
Pull Qualcomm clk driver updates from Bjorn Andersson: - Camera clock controller driver for Qualcomm QCS8300 - Correct wait_val values for a variety of Qualcomm GDSCs - Fix Qualcomm X Elite UFS clock settings - Allow clkaN to be optional in the Qualcomm RPMh clock controller driver if command db doesn't define it
2 parents 0af2f6b + 201bf08 commit b176dab

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13 files changed

+204
-9
lines changed

13 files changed

+204
-9
lines changed

‎Documentation/devicetree/bindings/clock/qcom,videocc.yaml

Lines changed: 20 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -14,6 +14,7 @@ description: |
1414
domains on Qualcomm SoCs.
1515
1616
See also::
17+
include/dt-bindings/clock/qcom,sm6350-videocc.h
1718
include/dt-bindings/clock/qcom,videocc-sc7180.h
1819
include/dt-bindings/clock/qcom,videocc-sc7280.h
1920
include/dt-bindings/clock/qcom,videocc-sdm845.h
@@ -26,6 +27,7 @@ properties:
2627
- qcom,sc7180-videocc
2728
- qcom,sc7280-videocc
2829
- qcom,sdm845-videocc
30+
- qcom,sm6350-videocc
2931
- qcom,sm8150-videocc
3032
- qcom,sm8250-videocc
3133

@@ -87,6 +89,24 @@ allOf:
8789
- const: bi_tcxo
8890
- const: bi_tcxo_ao
8991

92+
- if:
93+
properties:
94+
compatible:
95+
enum:
96+
- qcom,sm6350-videocc
97+
then:
98+
properties:
99+
clocks:
100+
items:
101+
- description: Video AHB clock from GCC
102+
- description: Board XO source
103+
- description: Sleep Clock source
104+
clock-names:
105+
items:
106+
- const: iface
107+
- const: bi_tcxo
108+
- const: sleep_clk
109+
90110
- if:
91111
properties:
92112
compatible:

‎drivers/clk/qcom/apcs-sdx55.c

Lines changed: 5 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -111,7 +111,11 @@ static int qcom_apcs_sdx55_clk_probe(struct platform_device *pdev)
111111
* driver, there seems to be no better place to do this. So do it here!
112112
*/
113113
cpu_dev = get_cpu_device(0);
114-
dev_pm_domain_attach(cpu_dev, true);
114+
ret = dev_pm_domain_attach(cpu_dev, true);
115+
if (ret) {
116+
dev_err_probe(dev, ret, "can't get PM domain: %d\n", ret);
117+
goto err;
118+
}
115119

116120
return 0;
117121

‎drivers/clk/qcom/camcc-sa8775p.c

Lines changed: 98 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -10,7 +10,7 @@
1010
#include <linux/pm_runtime.h>
1111
#include <linux/regmap.h>
1212

13-
#include <dt-bindings/clock/qcom,sa8775p-camcc.h>
13+
#include <dt-bindings/clock/qcom,qcs8300-camcc.h>
1414

1515
#include "clk-alpha-pll.h"
1616
#include "clk-branch.h"
@@ -1681,6 +1681,24 @@ static struct clk_branch cam_cc_sm_obs_clk = {
16811681
},
16821682
};
16831683

1684+
static struct clk_branch cam_cc_titan_top_accu_shift_clk = {
1685+
.halt_reg = 0x131f0,
1686+
.halt_check = BRANCH_HALT_VOTED,
1687+
.clkr = {
1688+
.enable_reg = 0x131f0,
1689+
.enable_mask = BIT(0),
1690+
.hw.init = &(const struct clk_init_data) {
1691+
.name = "cam_cc_titan_top_accu_shift_clk",
1692+
.parent_hws = (const struct clk_hw*[]) {
1693+
&cam_cc_xo_clk_src.clkr.hw,
1694+
},
1695+
.num_parents = 1,
1696+
.flags = CLK_SET_RATE_PARENT,
1697+
.ops = &clk_branch2_ops,
1698+
},
1699+
},
1700+
};
1701+
16841702
static struct gdsc cam_cc_titan_top_gdsc = {
16851703
.gdscr = 0x131bc,
16861704
.en_rest_wait_val = 0x2,
@@ -1775,6 +1793,7 @@ static struct clk_regmap *cam_cc_sa8775p_clocks[] = {
17751793
[CAM_CC_SLEEP_CLK_SRC] = &cam_cc_sleep_clk_src.clkr,
17761794
[CAM_CC_SLOW_AHB_CLK_SRC] = &cam_cc_slow_ahb_clk_src.clkr,
17771795
[CAM_CC_SM_OBS_CLK] = &cam_cc_sm_obs_clk.clkr,
1796+
[CAM_CC_TITAN_TOP_ACCU_SHIFT_CLK] = NULL,
17781797
[CAM_CC_XO_CLK_SRC] = &cam_cc_xo_clk_src.clkr,
17791798
[CAM_CC_QDSS_DEBUG_XO_CLK] = &cam_cc_qdss_debug_xo_clk.clkr,
17801799
};
@@ -1811,6 +1830,7 @@ static const struct qcom_cc_desc cam_cc_sa8775p_desc = {
18111830
};
18121831

18131832
static const struct of_device_id cam_cc_sa8775p_match_table[] = {
1833+
{ .compatible = "qcom,qcs8300-camcc" },
18141834
{ .compatible = "qcom,sa8775p-camcc" },
18151835
{ }
18161836
};
@@ -1841,10 +1861,83 @@ static int cam_cc_sa8775p_probe(struct platform_device *pdev)
18411861
clk_lucid_evo_pll_configure(&cam_cc_pll4, regmap, &cam_cc_pll4_config);
18421862
clk_lucid_evo_pll_configure(&cam_cc_pll5, regmap, &cam_cc_pll5_config);
18431863

1844-
/* Keep some clocks always enabled */
1845-
qcom_branch_set_clk_en(regmap, 0x13194); /* CAM_CC_CAMNOC_XO_CLK */
1846-
qcom_branch_set_clk_en(regmap, 0x131ec); /* CAM_CC_GDSC_CLK */
1847-
qcom_branch_set_clk_en(regmap, 0x13208); /* CAM_CC_SLEEP_CLK */
1864+
if (device_is_compatible(&pdev->dev, "qcom,qcs8300-camcc")) {
1865+
cam_cc_camnoc_axi_clk_src.cmd_rcgr = 0x13154;
1866+
cam_cc_camnoc_axi_clk.halt_reg = 0x1316c;
1867+
cam_cc_camnoc_axi_clk.clkr.enable_reg = 0x1316c;
1868+
cam_cc_camnoc_dcd_xo_clk.halt_reg = 0x13174;
1869+
cam_cc_camnoc_dcd_xo_clk.clkr.enable_reg = 0x13174;
1870+
1871+
cam_cc_csi0phytimer_clk_src.cmd_rcgr = 0x15054;
1872+
cam_cc_csi1phytimer_clk_src.cmd_rcgr = 0x15078;
1873+
cam_cc_csi2phytimer_clk_src.cmd_rcgr = 0x15098;
1874+
cam_cc_csid_clk_src.cmd_rcgr = 0x13134;
1875+
1876+
cam_cc_mclk0_clk_src.cmd_rcgr = 0x15000;
1877+
cam_cc_mclk1_clk_src.cmd_rcgr = 0x1501c;
1878+
cam_cc_mclk2_clk_src.cmd_rcgr = 0x15038;
1879+
1880+
cam_cc_fast_ahb_clk_src.cmd_rcgr = 0x13104;
1881+
cam_cc_slow_ahb_clk_src.cmd_rcgr = 0x1311c;
1882+
cam_cc_xo_clk_src.cmd_rcgr = 0x131b8;
1883+
cam_cc_sleep_clk_src.cmd_rcgr = 0x131d4;
1884+
1885+
cam_cc_core_ahb_clk.halt_reg = 0x131b4;
1886+
cam_cc_core_ahb_clk.clkr.enable_reg = 0x131b4;
1887+
1888+
cam_cc_cpas_ahb_clk.halt_reg = 0x130f4;
1889+
cam_cc_cpas_ahb_clk.clkr.enable_reg = 0x130f4;
1890+
cam_cc_cpas_fast_ahb_clk.halt_reg = 0x130fc;
1891+
cam_cc_cpas_fast_ahb_clk.clkr.enable_reg = 0x130fc;
1892+
1893+
cam_cc_csi0phytimer_clk.halt_reg = 0x1506c;
1894+
cam_cc_csi0phytimer_clk.clkr.enable_reg = 0x1506c;
1895+
cam_cc_csi1phytimer_clk.halt_reg = 0x15090;
1896+
cam_cc_csi1phytimer_clk.clkr.enable_reg = 0x15090;
1897+
cam_cc_csi2phytimer_clk.halt_reg = 0x150b0;
1898+
cam_cc_csi2phytimer_clk.clkr.enable_reg = 0x150b0;
1899+
cam_cc_csid_clk.halt_reg = 0x1314c;
1900+
cam_cc_csid_clk.clkr.enable_reg = 0x1314c;
1901+
cam_cc_csid_csiphy_rx_clk.halt_reg = 0x15074;
1902+
cam_cc_csid_csiphy_rx_clk.clkr.enable_reg = 0x15074;
1903+
cam_cc_csiphy0_clk.halt_reg = 0x15070;
1904+
cam_cc_csiphy0_clk.clkr.enable_reg = 0x15070;
1905+
cam_cc_csiphy1_clk.halt_reg = 0x15094;
1906+
cam_cc_csiphy1_clk.clkr.enable_reg = 0x15094;
1907+
cam_cc_csiphy2_clk.halt_reg = 0x150b4;
1908+
cam_cc_csiphy2_clk.clkr.enable_reg = 0x150b4;
1909+
1910+
cam_cc_mclk0_clk.halt_reg = 0x15018;
1911+
cam_cc_mclk0_clk.clkr.enable_reg = 0x15018;
1912+
cam_cc_mclk1_clk.halt_reg = 0x15034;
1913+
cam_cc_mclk1_clk.clkr.enable_reg = 0x15034;
1914+
cam_cc_mclk2_clk.halt_reg = 0x15050;
1915+
cam_cc_mclk2_clk.clkr.enable_reg = 0x15050;
1916+
cam_cc_qdss_debug_xo_clk.halt_reg = 0x1319c;
1917+
cam_cc_qdss_debug_xo_clk.clkr.enable_reg = 0x1319c;
1918+
1919+
cam_cc_titan_top_gdsc.gdscr = 0x131a0;
1920+
1921+
cam_cc_sa8775p_clocks[CAM_CC_CCI_3_CLK] = NULL;
1922+
cam_cc_sa8775p_clocks[CAM_CC_CCI_3_CLK_SRC] = NULL;
1923+
cam_cc_sa8775p_clocks[CAM_CC_CSI3PHYTIMER_CLK] = NULL;
1924+
cam_cc_sa8775p_clocks[CAM_CC_CSI3PHYTIMER_CLK_SRC] = NULL;
1925+
cam_cc_sa8775p_clocks[CAM_CC_CSIPHY3_CLK] = NULL;
1926+
cam_cc_sa8775p_clocks[CAM_CC_MCLK3_CLK] = NULL;
1927+
cam_cc_sa8775p_clocks[CAM_CC_MCLK3_CLK_SRC] = NULL;
1928+
cam_cc_sa8775p_clocks[CAM_CC_TITAN_TOP_ACCU_SHIFT_CLK] =
1929+
&cam_cc_titan_top_accu_shift_clk.clkr;
1930+
1931+
/* Keep some clocks always enabled */
1932+
qcom_branch_set_clk_en(regmap, 0x13178); /* CAM_CC_CAMNOC_XO_CLK */
1933+
qcom_branch_set_clk_en(regmap, 0x131d0); /* CAM_CC_GDSC_CLK */
1934+
qcom_branch_set_clk_en(regmap, 0x131ec); /* CAM_CC_SLEEP_CLK */
1935+
} else {
1936+
/* Keep some clocks always enabled */
1937+
qcom_branch_set_clk_en(regmap, 0x13194); /* CAM_CC_CAMNOC_XO_CLK */
1938+
qcom_branch_set_clk_en(regmap, 0x131ec); /* CAM_CC_GDSC_CLK */
1939+
qcom_branch_set_clk_en(regmap, 0x13208); /* CAM_CC_SLEEP_CLK */
1940+
}
18481941

18491942
ret = qcom_cc_really_probe(&pdev->dev, &cam_cc_sa8775p_desc, regmap);
18501943

‎drivers/clk/qcom/camcc-sm6350.c

Lines changed: 18 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1695,6 +1695,9 @@ static struct clk_branch camcc_sys_tmr_clk = {
16951695

16961696
static struct gdsc bps_gdsc = {
16971697
.gdscr = 0x6004,
1698+
.en_rest_wait_val = 0x2,
1699+
.en_few_wait_val = 0x2,
1700+
.clk_dis_wait_val = 0xf,
16981701
.pd = {
16991702
.name = "bps_gdsc",
17001703
},
@@ -1704,6 +1707,9 @@ static struct gdsc bps_gdsc = {
17041707

17051708
static struct gdsc ipe_0_gdsc = {
17061709
.gdscr = 0x7004,
1710+
.en_rest_wait_val = 0x2,
1711+
.en_few_wait_val = 0x2,
1712+
.clk_dis_wait_val = 0xf,
17071713
.pd = {
17081714
.name = "ipe_0_gdsc",
17091715
},
@@ -1713,6 +1719,9 @@ static struct gdsc ipe_0_gdsc = {
17131719

17141720
static struct gdsc ife_0_gdsc = {
17151721
.gdscr = 0x9004,
1722+
.en_rest_wait_val = 0x2,
1723+
.en_few_wait_val = 0x2,
1724+
.clk_dis_wait_val = 0xf,
17161725
.pd = {
17171726
.name = "ife_0_gdsc",
17181727
},
@@ -1721,6 +1730,9 @@ static struct gdsc ife_0_gdsc = {
17211730

17221731
static struct gdsc ife_1_gdsc = {
17231732
.gdscr = 0xa004,
1733+
.en_rest_wait_val = 0x2,
1734+
.en_few_wait_val = 0x2,
1735+
.clk_dis_wait_val = 0xf,
17241736
.pd = {
17251737
.name = "ife_1_gdsc",
17261738
},
@@ -1729,6 +1741,9 @@ static struct gdsc ife_1_gdsc = {
17291741

17301742
static struct gdsc ife_2_gdsc = {
17311743
.gdscr = 0xb004,
1744+
.en_rest_wait_val = 0x2,
1745+
.en_few_wait_val = 0x2,
1746+
.clk_dis_wait_val = 0xf,
17321747
.pd = {
17331748
.name = "ife_2_gdsc",
17341749
},
@@ -1737,6 +1752,9 @@ static struct gdsc ife_2_gdsc = {
17371752

17381753
static struct gdsc titan_top_gdsc = {
17391754
.gdscr = 0x14004,
1755+
.en_rest_wait_val = 0x2,
1756+
.en_few_wait_val = 0x2,
1757+
.clk_dis_wait_val = 0xf,
17401758
.pd = {
17411759
.name = "titan_top_gdsc",
17421760
},

‎drivers/clk/qcom/clk-rpmh.c

Lines changed: 11 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -66,6 +66,8 @@ struct clk_rpmh {
6666
struct clk_rpmh_desc {
6767
struct clk_hw **clks;
6868
size_t num_clks;
69+
/* RPMh clock clkaN are optional for this platform */
70+
bool clka_optional;
6971
};
7072

7173
static DEFINE_MUTEX(rpmh_clk_lock);
@@ -648,6 +650,7 @@ static struct clk_hw *sm8550_rpmh_clocks[] = {
648650
static const struct clk_rpmh_desc clk_rpmh_sm8550 = {
649651
.clks = sm8550_rpmh_clocks,
650652
.num_clks = ARRAY_SIZE(sm8550_rpmh_clocks),
653+
.clka_optional = true,
651654
};
652655

653656
static struct clk_hw *sm8650_rpmh_clocks[] = {
@@ -679,6 +682,7 @@ static struct clk_hw *sm8650_rpmh_clocks[] = {
679682
static const struct clk_rpmh_desc clk_rpmh_sm8650 = {
680683
.clks = sm8650_rpmh_clocks,
681684
.num_clks = ARRAY_SIZE(sm8650_rpmh_clocks),
685+
.clka_optional = true,
682686
};
683687

684688
static struct clk_hw *sc7280_rpmh_clocks[] = {
@@ -847,6 +851,7 @@ static struct clk_hw *sm8750_rpmh_clocks[] = {
847851
static const struct clk_rpmh_desc clk_rpmh_sm8750 = {
848852
.clks = sm8750_rpmh_clocks,
849853
.num_clks = ARRAY_SIZE(sm8750_rpmh_clocks),
854+
.clka_optional = true,
850855
};
851856

852857
static struct clk_hw *of_clk_rpmh_hw_get(struct of_phandle_args *clkspec,
@@ -890,6 +895,12 @@ static int clk_rpmh_probe(struct platform_device *pdev)
890895
rpmh_clk = to_clk_rpmh(hw_clks[i]);
891896
res_addr = cmd_db_read_addr(rpmh_clk->res_name);
892897
if (!res_addr) {
898+
hw_clks[i] = NULL;
899+
900+
if (desc->clka_optional &&
901+
!strncmp(rpmh_clk->res_name, "clka", sizeof("clka") - 1))
902+
continue;
903+
893904
dev_err(&pdev->dev, "missing RPMh resource address for %s\n",
894905
rpmh_clk->res_name);
895906
return -ENODEV;

‎drivers/clk/qcom/dispcc-sm6350.c

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -681,6 +681,9 @@ static struct clk_branch disp_cc_xo_clk = {
681681

682682
static struct gdsc mdss_gdsc = {
683683
.gdscr = 0x1004,
684+
.en_rest_wait_val = 0x2,
685+
.en_few_wait_val = 0x2,
686+
.clk_dis_wait_val = 0xf,
684687
.pd = {
685688
.name = "mdss_gdsc",
686689
},

‎drivers/clk/qcom/gcc-msm8939.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -432,7 +432,7 @@ static const struct parent_map gcc_xo_gpll0_gpll1a_gpll6_sleep_map[] = {
432432
{ P_XO, 0 },
433433
{ P_GPLL0, 1 },
434434
{ P_GPLL1_AUX, 2 },
435-
{ P_GPLL6, 2 },
435+
{ P_GPLL6, 3 },
436436
{ P_SLEEP_CLK, 6 },
437437
};
438438

@@ -1113,7 +1113,7 @@ static struct clk_rcg2 jpeg0_clk_src = {
11131113
};
11141114

11151115
static const struct freq_tbl ftbl_gcc_camss_mclk0_1_clk[] = {
1116-
F(24000000, P_GPLL0, 1, 1, 45),
1116+
F(24000000, P_GPLL6, 1, 1, 45),
11171117
F(66670000, P_GPLL0, 12, 0, 0),
11181118
{ }
11191119
};

‎drivers/clk/qcom/gcc-sm6350.c

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2320,6 +2320,9 @@ static struct clk_branch gcc_video_xo_clk = {
23202320

23212321
static struct gdsc usb30_prim_gdsc = {
23222322
.gdscr = 0x1a004,
2323+
.en_rest_wait_val = 0x2,
2324+
.en_few_wait_val = 0x2,
2325+
.clk_dis_wait_val = 0xf,
23232326
.pd = {
23242327
.name = "usb30_prim_gdsc",
23252328
},
@@ -2328,6 +2331,9 @@ static struct gdsc usb30_prim_gdsc = {
23282331

23292332
static struct gdsc ufs_phy_gdsc = {
23302333
.gdscr = 0x3a004,
2334+
.en_rest_wait_val = 0x2,
2335+
.en_few_wait_val = 0x2,
2336+
.clk_dis_wait_val = 0xf,
23312337
.pd = {
23322338
.name = "ufs_phy_gdsc",
23332339
},

‎drivers/clk/qcom/gcc-sm8650.c

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3817,7 +3817,9 @@ static int gcc_sm8650_probe(struct platform_device *pdev)
38173817
qcom_branch_set_clk_en(regmap, 0x32004); /* GCC_VIDEO_AHB_CLK */
38183818
qcom_branch_set_clk_en(regmap, 0x32030); /* GCC_VIDEO_XO_CLK */
38193819

3820+
/* FORCE_MEM_CORE_ON for ufs phy ice core and gcc ufs phy axi clocks */
38203821
qcom_branch_set_force_mem_core(regmap, gcc_ufs_phy_ice_core_clk, true);
3822+
qcom_branch_set_force_mem_core(regmap, gcc_ufs_phy_axi_clk, true);
38213823

38223824
/* Clear GDSC_SLEEP_ENA_VOTE to stop votes being auto-removed in sleep. */
38233825
regmap_write(regmap, 0x52150, 0x0);

‎drivers/clk/qcom/gcc-sm8750.c

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3244,8 +3244,9 @@ static int gcc_sm8750_probe(struct platform_device *pdev)
32443244
regmap_update_bits(regmap, 0x52010, BIT(20), BIT(20));
32453245
regmap_update_bits(regmap, 0x52010, BIT(21), BIT(21));
32463246

3247-
/* FORCE_MEM_CORE_ON for ufs phy ice core clocks */
3247+
/* FORCE_MEM_CORE_ON for ufs phy ice core and gcc ufs phy axi clocks */
32483248
qcom_branch_set_force_mem_core(regmap, gcc_ufs_phy_ice_core_clk, true);
3249+
qcom_branch_set_force_mem_core(regmap, gcc_ufs_phy_axi_clk, true);
32493250

32503251
return qcom_cc_really_probe(&pdev->dev, &gcc_sm8750_desc, regmap);
32513252
}

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