Skip to content

Commit a9024a3

Browse files
pbrkrgeertu
pbrkr
authored and
geertu
committed
pinctrl: renesas: rzg2l: Clean up and refactor OEN read/write functions
The variable naming in the various OEN functions has been confusing. We were passing the _pin & bit variables from rzg2l_pinctrl_pinconf_get() and rzg2l_pinctrl_pinconf_set() as the offset & pin argument to the oen_read() and oen_write() functions. This doesn't make sense, the first of these isn't actually an offset and the second is not needed for RZ/V2H but leads to confusion with the bit variable used within these functions. To tidy this up, instead pass the _pin variable directly to the oen_read() and oen_write() functions with consistent naming. Then rzg3s_read_oen() and rzg3s_write_oen() can use macros to get the port and pin numbers it needs. Instead of passing the pin capabilities into oen_read() and oen_write(), check that the pin supports OEN before calling these functions. Also, merge rzg3s_oen_is_supported() into rzg3s_pin_to_oen_bit() to give a single translation function which returns an error if the pin doesn't support OEN. While we're here, remove an unnecessary branch and clarify the variable naming. Lastly, check that we are not dealing with a dedicated pin before calling RZG2L_PIN_ID_TO_{PORT,PIN}(). Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20240625200316.4282-3-paul.barker.ct@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
1 parent 07dd08c commit a9024a3

File tree

1 file changed

+36
-49
lines changed

1 file changed

+36
-49
lines changed

‎drivers/pinctrl/renesas/pinctrl-rzg2l.c

Lines changed: 36 additions & 49 deletions
Original file line numberDiff line numberDiff line change
@@ -294,8 +294,8 @@ struct rzg2l_pinctrl_data {
294294
#endif
295295
void (*pwpr_pfc_lock_unlock)(struct rzg2l_pinctrl *pctrl, bool lock);
296296
void (*pmc_writeb)(struct rzg2l_pinctrl *pctrl, u8 val, u16 offset);
297-
u32 (*oen_read)(struct rzg2l_pinctrl *pctrl, u32 caps, u32 offset, u8 pin);
298-
int (*oen_write)(struct rzg2l_pinctrl *pctrl, u32 caps, u32 offset, u8 pin, u8 oen);
297+
u32 (*oen_read)(struct rzg2l_pinctrl *pctrl, unsigned int _pin);
298+
int (*oen_write)(struct rzg2l_pinctrl *pctrl, unsigned int _pin, u8 oen);
299299
int (*hw_to_bias_param)(unsigned int val);
300300
int (*bias_param_to_hw)(enum pin_config_param param);
301301
};
@@ -999,53 +999,46 @@ static bool rzg2l_ds_is_supported(struct rzg2l_pinctrl *pctrl, u32 caps,
999999
return false;
10001000
}
10011001

1002-
static bool rzg3s_oen_is_supported(u32 caps, u8 pin, u8 max_pin)
1002+
static int rzg3s_pin_to_oen_bit(struct rzg2l_pinctrl *pctrl, unsigned int _pin)
10031003
{
1004-
if (!(caps & PIN_CFG_OEN))
1005-
return false;
1006-
1007-
if (pin > max_pin)
1008-
return false;
1004+
u64 *pin_data = pctrl->desc.pins[_pin].drv_data;
1005+
u8 port, pin, bit;
10091006

1010-
return true;
1011-
}
1007+
if (*pin_data & RZG2L_SINGLE_PIN)
1008+
return -EINVAL;
10121009

1013-
static u8 rzg3s_pin_to_oen_bit(u32 offset, u8 pin, u8 max_port)
1014-
{
1015-
if (pin)
1016-
pin *= 2;
1010+
port = RZG2L_PIN_ID_TO_PORT(_pin);
1011+
pin = RZG2L_PIN_ID_TO_PIN(_pin);
1012+
if (pin > pctrl->data->hwcfg->oen_max_pin)
1013+
return -EINVAL;
10171014

1018-
if (offset / RZG2L_PINS_PER_PORT == max_port)
1019-
pin += 1;
1015+
bit = pin * 2;
1016+
if (port == pctrl->data->hwcfg->oen_max_port)
1017+
bit += 1;
10201018

1021-
return pin;
1019+
return bit;
10221020
}
10231021

1024-
static u32 rzg3s_oen_read(struct rzg2l_pinctrl *pctrl, u32 caps, u32 offset, u8 pin)
1022+
static u32 rzg3s_oen_read(struct rzg2l_pinctrl *pctrl, unsigned int _pin)
10251023
{
1026-
u8 max_port = pctrl->data->hwcfg->oen_max_port;
1027-
u8 max_pin = pctrl->data->hwcfg->oen_max_pin;
1028-
u8 bit;
1029-
1030-
if (!rzg3s_oen_is_supported(caps, pin, max_pin))
1031-
return 0;
1024+
int bit;
10321025

1033-
bit = rzg3s_pin_to_oen_bit(offset, pin, max_port);
1026+
bit = rzg3s_pin_to_oen_bit(pctrl, _pin);
1027+
if (bit < 0)
1028+
return bit;
10341029

10351030
return !(readb(pctrl->base + ETH_MODE) & BIT(bit));
10361031
}
10371032

1038-
static int rzg3s_oen_write(struct rzg2l_pinctrl *pctrl, u32 caps, u32 offset, u8 pin, u8 oen)
1033+
static int rzg3s_oen_write(struct rzg2l_pinctrl *pctrl, unsigned int _pin, u8 oen)
10391034
{
1040-
u8 max_port = pctrl->data->hwcfg->oen_max_port;
1041-
u8 max_pin = pctrl->data->hwcfg->oen_max_pin;
10421035
unsigned long flags;
1043-
u8 val, bit;
1044-
1045-
if (!rzg3s_oen_is_supported(caps, pin, max_pin))
1046-
return -EINVAL;
1036+
int bit;
1037+
u8 val;
10471038

1048-
bit = rzg3s_pin_to_oen_bit(offset, pin, max_port);
1039+
bit = rzg3s_pin_to_oen_bit(pctrl, _pin);
1040+
if (bit < 0)
1041+
return bit;
10491042

10501043
spin_lock_irqsave(&pctrl->lock, flags);
10511044
val = readb(pctrl->base + ETH_MODE);
@@ -1124,12 +1117,12 @@ static int rzv2h_bias_param_to_hw(enum pin_config_param param)
11241117
return -EINVAL;
11251118
}
11261119

1127-
static u8 rzv2h_pin_to_oen_bit(struct rzg2l_pinctrl *pctrl, u32 offset)
1120+
static u8 rzv2h_pin_to_oen_bit(struct rzg2l_pinctrl *pctrl, unsigned int _pin)
11281121
{
11291122
static const char * const pin_names[] = { "ET0_TXC_TXCLK", "ET1_TXC_TXCLK",
11301123
"XSPI0_RESET0N", "XSPI0_CS0N",
11311124
"XSPI0_CKN", "XSPI0_CKP" };
1132-
const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset];
1125+
const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[_pin];
11331126
unsigned int i;
11341127

11351128
for (i = 0; i < ARRAY_SIZE(pin_names); i++) {
@@ -1141,30 +1134,24 @@ static u8 rzv2h_pin_to_oen_bit(struct rzg2l_pinctrl *pctrl, u32 offset)
11411134
return 0;
11421135
}
11431136

1144-
static u32 rzv2h_oen_read(struct rzg2l_pinctrl *pctrl, u32 caps, u32 offset, u8 pin)
1137+
static u32 rzv2h_oen_read(struct rzg2l_pinctrl *pctrl, unsigned int _pin)
11451138
{
11461139
u8 bit;
11471140

1148-
if (!(caps & PIN_CFG_OEN))
1149-
return 0;
1150-
1151-
bit = rzv2h_pin_to_oen_bit(pctrl, offset);
1141+
bit = rzv2h_pin_to_oen_bit(pctrl, _pin);
11521142

11531143
return !(readb(pctrl->base + PFC_OEN) & BIT(bit));
11541144
}
11551145

1156-
static int rzv2h_oen_write(struct rzg2l_pinctrl *pctrl, u32 caps, u32 offset, u8 pin, u8 oen)
1146+
static int rzv2h_oen_write(struct rzg2l_pinctrl *pctrl, unsigned int _pin, u8 oen)
11571147
{
11581148
const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg;
11591149
const struct rzg2l_register_offsets *regs = &hwcfg->regs;
11601150
unsigned long flags;
11611151
u8 val, bit;
11621152
u8 pwpr;
11631153

1164-
if (!(caps & PIN_CFG_OEN))
1165-
return -EINVAL;
1166-
1167-
bit = rzv2h_pin_to_oen_bit(pctrl, offset);
1154+
bit = rzv2h_pin_to_oen_bit(pctrl, _pin);
11681155
spin_lock_irqsave(&pctrl->lock, flags);
11691156
val = readb(pctrl->base + PFC_OEN);
11701157
if (oen)
@@ -1220,9 +1207,9 @@ static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev,
12201207
break;
12211208

12221209
case PIN_CONFIG_OUTPUT_ENABLE:
1223-
if (!pctrl->data->oen_read)
1210+
if (!pctrl->data->oen_read || !(cfg & PIN_CFG_OEN))
12241211
return -EOPNOTSUPP;
1225-
arg = pctrl->data->oen_read(pctrl, cfg, _pin, bit);
1212+
arg = pctrl->data->oen_read(pctrl, _pin);
12261213
if (!arg)
12271214
return -EINVAL;
12281215
break;
@@ -1361,9 +1348,9 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev,
13611348

13621349
case PIN_CONFIG_OUTPUT_ENABLE:
13631350
arg = pinconf_to_config_argument(_configs[i]);
1364-
if (!pctrl->data->oen_write)
1351+
if (!pctrl->data->oen_write || !(cfg & PIN_CFG_OEN))
13651352
return -EOPNOTSUPP;
1366-
ret = pctrl->data->oen_write(pctrl, cfg, _pin, bit, !!arg);
1353+
ret = pctrl->data->oen_write(pctrl, _pin, !!arg);
13671354
if (ret)
13681355
return ret;
13691356
break;

0 commit comments

Comments
 (0)