Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

Pull clk updates from Stephen Boyd:
 "This has been a semi-quiet cycle. The core framework remains unchanged
  this time around.

  In terms of shiny new code though, we have support for the SpacemiT K1
  SoC, Sophgo SG2044, and T-HEAD TH1520 VO clk drivers joining the usual
  silicon players like Qualcomm, Samsung, Allwinner, and Renesas.

  Surprisingly, the Qualcomm pile was smaller than usual but that is
  likely because they put one SoC support inside a driver for a
  different SoC that is very similar.

  Other than all those new clk drivers there are the usual clk data
  updates to fix parents, frequency tables, and add missing clks along
  with some Kconfig changes to make compile testing simpler and even
  more DT binding conversions to boot.

  The exciting part is still the new SoC support like SpacemiT and
  Sophgo support though, which really dominate the diffstat because they
  introduce a whole new silicon vendor clk driver.

  New Drivers:
   - Camera clock controller driver for Qualcomm QCS8300
   - DE (display engine) 3.3 clocks on Allwinner H616
   - Samsung ExynosAutov920 CPU cluster CL0, CL1 and CL2 clock controllers
   - Video Output (VO) subsystem clk controller in the T-HEAD TH1520 SoC
   - Clock driver for Sophgo SG2044
   - Clock driver for SpacemiT K1 SoC
   - Renesas RZ/V2N (R9A09G056) SoC clk driver

  Updates:
   - Correct data in various SoC clk drivers
   - Allow clkaN to be optional in the Qualcomm RPMh clock controller
     driver if command db doesn't define it
   - Change Kconfig options to not enable by default during compile
     testing
   - Add missing clks in various SoC clk drivers
   - Remove some duplicate clk DT bindings and convert some more to
     YAML"

* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (93 commits)
  clk: qcom: gcc-x1e80100: Set FORCE MEM CORE for UFS clocks
  clk: qcom: gcc: Set FORCE_MEM_CORE_ON for gcc_ufs_axi_clk for 8650/8750
  clk: qcom: rpmh: make clkaN optional
  clk: qcom: Add support for Camera Clock Controller on QCS8300
  clk: rockchip: rk3528: add slab.h header include
  clk: rockchip: rk3576: add missing slab.h include
  clk: meson: Do not enable by default during compile testing
  clk: meson-g12a: add missing fclk_div2 to spicc
  clk: qcom: gcc-msm8939: Fix mclk0 & mclk1 for 24 MHz
  clk: rockchip: rename gate-grf clk file
  clk: rockchip: rename branch_muxgrf to branch_grf_mux
  clk: sunxi-ng: ccu: add Display Engine 3.3 (DE33) support
  dt-bindings: allwinner: add H616 DE33 clock binding
  clk: samsung: correct clock summary for hsi1 block
  dt-bindings: clock: add SM6350 QCOM video clock bindings
  clk: rockchip: Pass NULL as reg pointer when registering GRF MMC clocks
  clk: sunxi-ng: h616: Add LVDS reset for LCD TCON
  dt-bindings: clock: sun50i-h616-ccu: Add LVDS reset
  clk: rockchip: rk3036: mark ddrphy as critical
  clk: rockchip: rk3036: fix implementation of usb480m clock mux
  ...

Author: torvalds

Documentation/devicetree/bindings/clock/allwinner,sun8i-a83t-de2-clk.yaml

@@ -25,6 +25,7 @@ properties:
       - const: allwinner,sun50i-a64-de2-clk
       - const: allwinner,sun50i-h5-de2-clk
       - const: allwinner,sun50i-h6-de3-clk
+      - const: allwinner,sun50i-h616-de33-clk
       - items:
           - const: allwinner,sun8i-r40-de2-clk
           - const: allwinner,sun8i-h3-de2-clk

Documentation/devicetree/bindings/clock/brcm,bcm2835-aux-clock.txt

@@ -0,0 +1,47 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/brcm,bcm2835-aux-clock.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Broadcom BCM2835 auxiliary peripheral clock
+
+maintainers:
+  - Stefan Wahren <wahrenst@gmx.net>
+  - Raspberry Pi Kernel Maintenance <kernel-list@raspberrypi.com>
+
+description:
+  The auxiliary peripherals (UART, SPI1, and SPI2) have a small register
+  area controlling clock gating to the peripherals, and providing an IRQ
+  status register.
+
+properties:
+  compatible:
+    const: brcm,bcm2835-aux
+
+  reg:
+    maxItems: 1
+
+  "#clock-cells":
+    const: 1
+
+  clocks:
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+  - "#clock-cells"
+  - clocks
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/bcm2835.h>
+    clock@7e215000 {
+        compatible = "brcm,bcm2835-aux";
+        reg = <0x7e215000 0x8>;
+        #clock-cells = <1>;
+        clocks = <&clocks BCM2835_CLOCK_VPU>;
+    };

Documentation/devicetree/bindings/clock/brcm,bcm2835-aux-clock.yaml

@@ -0,0 +1,58 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/fsl,vf610-ccm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Clock for Freescale Vybrid VF610 SOC
+
+description:
+  The clock consumer should specify the desired clock by having the clock
+  ID in its "clocks" phandle cell. See include/dt-bindings/clock/vf610-clock.h
+  for the full list of VF610 clock IDs
+
+maintainers:
+  - Frank Li <Frank.Li@nxp.com>
+
+properties:
+  compatible:
+    const: fsl,vf610-ccm
+
+  reg:
+    maxItems: 1
+
+  '#clock-cells':
+    const: 1
+
+  clocks:
+    items:
+      - description: external crystal oscillator 32KHz, recommended
+      - description: external crystal oscillator 24MHz, recommended
+      - description: audio
+      - description: enet
+    minItems: 2
+
+  clock-names:
+    items:
+      - const: sxosc
+      - const: fxosc
+      - const: enet_ext
+      - const: audio_ext
+    minItems: 2
+
+required:
+  - compatible
+  - reg
+
+additionalProperties: false
+
+examples:
+  - |
+    clock-controller@4006b000 {
+        compatible = "fsl,vf610-ccm";
+        reg = <0x4006b000 0x1000>;
+        #clock-cells = <1>;
+        clocks = <&sxosc>, <&fxosc>;
+        clock-names = "sxosc", "fxosc";
+    };
+

Documentation/devicetree/bindings/clock/fsl,vf610-ccm.yaml

@@ -14,6 +14,7 @@ description: |
   domains on Qualcomm SoCs.
 
   See also::
+    include/dt-bindings/clock/qcom,sm6350-videocc.h
     include/dt-bindings/clock/qcom,videocc-sc7180.h
     include/dt-bindings/clock/qcom,videocc-sc7280.h
     include/dt-bindings/clock/qcom,videocc-sdm845.h
@@ -26,6 +27,7 @@ properties:
       - qcom,sc7180-videocc
       - qcom,sc7280-videocc
       - qcom,sdm845-videocc
+      - qcom,sm6350-videocc
       - qcom,sm8150-videocc
       - qcom,sm8250-videocc
 
@@ -87,6 +89,24 @@ allOf:
             - const: bi_tcxo
             - const: bi_tcxo_ao
 
+  - if:
+      properties:
+        compatible:
+          enum:
+            - qcom,sm6350-videocc
+    then:
+      properties:
+        clocks:
+          items:
+            - description: Video AHB clock from GCC
+            - description: Board XO source
+            - description: Sleep Clock source
+        clock-names:
+          items:
+            - const: iface
+            - const: bi_tcxo
+            - const: sleep_clk
+
   - if:
       properties:
         compatible:

Documentation/devicetree/bindings/clock/maxim,max77686.txt

@@ -4,13 +4,13 @@
 $id: http://devicetree.org/schemas/clock/renesas,rzv2h-cpg.yaml#
 $schema: http://devicetree.org/meta-schemas/core.yaml#
 
-title: Renesas RZ/{G3E,V2H(P)} Clock Pulse Generator (CPG)
+title: Renesas RZ/{G3E,V2H(P),V2N} Clock Pulse Generator (CPG)
 
 maintainers:
   - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
 
 description:
-  On Renesas RZ/{G3E,V2H(P)} SoCs, the CPG (Clock Pulse Generator) handles
+  On Renesas RZ/{G3E,V2H(P),V2N} SoCs, the CPG (Clock Pulse Generator) handles
   generation and control of clock signals for the IP modules, generation and
   control of resets, and control over booting, low power consumption and power
   supply domains.
@@ -19,6 +19,7 @@ properties:
   compatible:
     enum:
       - renesas,r9a09g047-cpg # RZ/G3E
+      - renesas,r9a09g056-cpg # RZ/V2N
       - renesas,r9a09g057-cpg # RZ/V2H
 
   reg: