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Merge tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux
Pull arm64 fixes from Will Deacon: "Here is a (hopefully) final round of arm64 fixes for 6.12 that address some user-visible floating point register corruption. Both of the Marks have been working on this for a couple of weeks and we've ended up in a position where SVE is solid but SME still has enough pending issues that the most pragmatic solution for the release and stable backports is to disable the feature. Yes, it's a shame, but the hardware is rare as hen's teeth at the moment and we're better off getting back to a known good state before fixing it all properly. We're also improving the selftests for 6.13 to help avoid merging broken code in the future. Anyway, the good news is that we're removing a lot more code than we're adding. Summary: - Fix handling of SVE traps from userspace on preemptible kernels when converting the saved floating point state into SVE state. - Remove broken support for the SMCCCv1.3 "SVE discard hint" optimisation. - Disable SME support, as the current support code suffers from numerous issues around signal delivery, ptrace access and context-switch which can lead to user-visible corruption of the register state" * tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux: arm64: Kconfig: Make SME depend on BROKEN for now arm64: smccc: Remove broken support for SMCCCv1.3 SVE discard hint arm64/sve: Discard stale CPU state when handling SVE traps
2 parents 51b4786 + 81235ae commit 9ea7eda

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arch/arm64/Kconfig

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Original file line numberDiff line numberDiff line change
@@ -2214,6 +2214,7 @@ config ARM64_SME
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bool "ARM Scalable Matrix Extension support"
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default y
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depends on ARM64_SVE
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depends on BROKEN
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help
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The Scalable Matrix Extension (SME) is an extension to the AArch64
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execution state which utilises a substantial subset of the SVE

arch/arm64/kernel/fpsimd.c

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@@ -1367,6 +1367,7 @@ static void sve_init_regs(void)
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} else {
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fpsimd_to_sve(current);
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current->thread.fp_type = FP_STATE_SVE;
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fpsimd_flush_task_state(current);
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}
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}
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arch/arm64/kernel/smccc-call.S

Lines changed: 3 additions & 32 deletions
Original file line numberDiff line numberDiff line change
@@ -7,48 +7,19 @@
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#include <asm/asm-offsets.h>
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#include <asm/assembler.h>
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#include <asm/thread_info.h>
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/*
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* If we have SMCCC v1.3 and (as is likely) no SVE state in
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* the registers then set the SMCCC hint bit to say there's no
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* need to preserve it. Do this by directly adjusting the SMCCC
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* function value which is already stored in x0 ready to be called.
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*/
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SYM_FUNC_START(__arm_smccc_sve_check)
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ldr_l x16, smccc_has_sve_hint
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cbz x16, 2f
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get_current_task x16
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ldr x16, [x16, #TSK_TI_FLAGS]
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tbnz x16, #TIF_FOREIGN_FPSTATE, 1f // Any live FP state?
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tbnz x16, #TIF_SVE, 2f // Does that state include SVE?
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1: orr x0, x0, ARM_SMCCC_1_3_SVE_HINT
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2: ret
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SYM_FUNC_END(__arm_smccc_sve_check)
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EXPORT_SYMBOL(__arm_smccc_sve_check)
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.macro SMCCC instr
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stp x29, x30, [sp, #-16]!
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mov x29, sp
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alternative_if ARM64_SVE
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bl __arm_smccc_sve_check
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alternative_else_nop_endif
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\instr #0
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ldr x4, [sp, #16]
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ldr x4, [sp]
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stp x0, x1, [x4, #ARM_SMCCC_RES_X0_OFFS]
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stp x2, x3, [x4, #ARM_SMCCC_RES_X2_OFFS]
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ldr x4, [sp, #24]
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ldr x4, [sp, #8]
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cbz x4, 1f /* no quirk structure */
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ldr x9, [x4, #ARM_SMCCC_QUIRK_ID_OFFS]
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cmp x9, #ARM_SMCCC_QUIRK_QCOM_A6
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b.ne 1f
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str x6, [x4, ARM_SMCCC_QUIRK_STATE_OFFS]
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1: ldp x29, x30, [sp], #16
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ret
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1: ret
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.endm
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/*

drivers/firmware/smccc/smccc.c

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Original file line numberDiff line numberDiff line change
@@ -16,7 +16,6 @@ static u32 smccc_version = ARM_SMCCC_VERSION_1_0;
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static enum arm_smccc_conduit smccc_conduit = SMCCC_CONDUIT_NONE;
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bool __ro_after_init smccc_trng_available = false;
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u64 __ro_after_init smccc_has_sve_hint = false;
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s32 __ro_after_init smccc_soc_id_version = SMCCC_RET_NOT_SUPPORTED;
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s32 __ro_after_init smccc_soc_id_revision = SMCCC_RET_NOT_SUPPORTED;
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@@ -28,9 +27,6 @@ void __init arm_smccc_version_init(u32 version, enum arm_smccc_conduit conduit)
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smccc_conduit = conduit;
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smccc_trng_available = smccc_probe_trng();
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if (IS_ENABLED(CONFIG_ARM64_SVE) &&
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smccc_version >= ARM_SMCCC_VERSION_1_3)
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smccc_has_sve_hint = true;
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if ((smccc_version >= ARM_SMCCC_VERSION_1_2) &&
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(smccc_conduit != SMCCC_CONDUIT_NONE)) {

include/linux/arm-smccc.h

Lines changed: 3 additions & 29 deletions
Original file line numberDiff line numberDiff line change
@@ -315,8 +315,6 @@ u32 arm_smccc_get_version(void);
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void __init arm_smccc_version_init(u32 version, enum arm_smccc_conduit conduit);
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extern u64 smccc_has_sve_hint;
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/**
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* arm_smccc_get_soc_id_version()
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*
@@ -414,15 +412,6 @@ struct arm_smccc_quirk {
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} state;
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};
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/**
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* __arm_smccc_sve_check() - Set the SVE hint bit when doing SMC calls
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*
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* Sets the SMCCC hint bit to indicate if there is live state in the SVE
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* registers, this modifies x0 in place and should never be called from C
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* code.
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*/
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asmlinkage unsigned long __arm_smccc_sve_check(unsigned long x0);
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/**
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* __arm_smccc_smc() - make SMC calls
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* @a0-a7: arguments passed in registers 0 to 7
@@ -490,20 +479,6 @@ asmlinkage void __arm_smccc_hvc(unsigned long a0, unsigned long a1,
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491480
#endif
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/* nVHE hypervisor doesn't have a current thread so needs separate checks */
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#if defined(CONFIG_ARM64_SVE) && !defined(__KVM_NVHE_HYPERVISOR__)
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496-
#define SMCCC_SVE_CHECK ALTERNATIVE("nop \n", "bl __arm_smccc_sve_check \n", \
497-
ARM64_SVE)
498-
#define smccc_sve_clobbers "x16", "x30", "cc",
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500-
#else
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502-
#define SMCCC_SVE_CHECK
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#define smccc_sve_clobbers
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#endif
506-
507482
#define __constraint_read_2 "r" (arg0)
508483
#define __constraint_read_3 __constraint_read_2, "r" (arg1)
509484
#define __constraint_read_4 __constraint_read_3, "r" (arg2)
@@ -574,12 +549,11 @@ asmlinkage void __arm_smccc_hvc(unsigned long a0, unsigned long a1,
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register unsigned long r3 asm("r3"); \
575550
CONCATENATE(__declare_arg_, \
576551
COUNT_ARGS(__VA_ARGS__))(__VA_ARGS__); \
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asm volatile(SMCCC_SVE_CHECK \
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inst "\n" : \
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asm volatile(inst "\n" : \
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"=r" (r0), "=r" (r1), "=r" (r2), "=r" (r3) \
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: CONCATENATE(__constraint_read_, \
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COUNT_ARGS(__VA_ARGS__)) \
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: smccc_sve_clobbers "memory"); \
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: "memory"); \
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if (___res) \
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*___res = (typeof(*___res)){r0, r1, r2, r3}; \
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} while (0)
@@ -628,7 +602,7 @@ asmlinkage void __arm_smccc_hvc(unsigned long a0, unsigned long a1,
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asm ("" : \
629603
: CONCATENATE(__constraint_read_, \
630604
COUNT_ARGS(__VA_ARGS__)) \
631-
: smccc_sve_clobbers "memory"); \
605+
: "memory"); \
632606
if (___res) \
633607
___res->a0 = SMCCC_RET_NOT_SUPPORTED; \
634608
} while (0)

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