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bnilawarjnikula
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drm/i915: Disable RPG during live selftest
The Forcewake timeout issue has been observed on Gen 12.0 and above. To address this, disable Render Power-Gating (RPG) during live self-tests for these generations. The temporary workaround 'drm/i915/mtl: do not enable render power-gating on MTL' disables RPG globally, which is unnecessary since the issues were only seen during self-tests. v2: take runtime pm wakeref Closes: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9413 Fixes: 25e7976 ("drm/i915/mtl: do not enable render power-gating on MTL") Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Andi Shyti <andi.shyti@intel.com> Cc: Andrzej Hajda <andrzej.hajda@intel.com> Signed-off-by: Badal Nilawar <badal.nilawar@intel.com> Signed-off-by: Sk Anirban <sk.anirban@intel.com> Reviewed-by: Karthik Poosa <karthik.poosa@intel.com> Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20250310152821.2931678-1-sk.anirban@intel.com (cherry picked from commit 0a4ae87) Signed-off-by: Jani Nikula <jani.nikula@intel.com>
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lines changed

2 files changed

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lines changed

drivers/gpu/drm/i915/gt/intel_rc6.c

Lines changed: 4 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -117,21 +117,10 @@ static void gen11_rc6_enable(struct intel_rc6 *rc6)
117117
GEN6_RC_CTL_RC6_ENABLE |
118118
GEN6_RC_CTL_EI_MODE(1);
119119

120-
/*
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* BSpec 52698 - Render powergating must be off.
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* FIXME BSpec is outdated, disabling powergating for MTL is just
123-
* temporary wa and should be removed after fixing real cause
124-
* of forcewake timeouts.
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*/
126-
if (IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 74)))
127-
pg_enable =
128-
GEN9_MEDIA_PG_ENABLE |
129-
GEN11_MEDIA_SAMPLER_PG_ENABLE;
130-
else
131-
pg_enable =
132-
GEN9_RENDER_PG_ENABLE |
133-
GEN9_MEDIA_PG_ENABLE |
134-
GEN11_MEDIA_SAMPLER_PG_ENABLE;
120+
pg_enable =
121+
GEN9_RENDER_PG_ENABLE |
122+
GEN9_MEDIA_PG_ENABLE |
123+
GEN11_MEDIA_SAMPLER_PG_ENABLE;
135124

136125
if (GRAPHICS_VER(gt->i915) >= 12 && !IS_DG1(gt->i915)) {
137126
for (i = 0; i < I915_MAX_VCS; i++)

drivers/gpu/drm/i915/selftests/i915_selftest.c

Lines changed: 18 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -23,7 +23,9 @@
2323

2424
#include <linux/random.h>
2525

26+
#include "gt/intel_gt.h"
2627
#include "gt/intel_gt_pm.h"
28+
#include "gt/intel_gt_regs.h"
2729
#include "gt/uc/intel_gsc_fw.h"
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2931
#include "i915_driver.h"
@@ -253,11 +255,27 @@ int i915_mock_selftests(void)
253255
int i915_live_selftests(struct pci_dev *pdev)
254256
{
255257
struct drm_i915_private *i915 = pdev_to_i915(pdev);
258+
struct intel_uncore *uncore = &i915->uncore;
256259
int err;
260+
u32 pg_enable;
261+
intel_wakeref_t wakeref;
257262

258263
if (!i915_selftest.live)
259264
return 0;
260265

266+
/*
267+
* FIXME Disable render powergating, this is temporary wa and should be removed
268+
* after fixing real cause of forcewake timeouts.
269+
*/
270+
with_intel_runtime_pm(uncore->rpm, wakeref) {
271+
if (IS_GFX_GT_IP_RANGE(to_gt(i915), IP_VER(12, 00), IP_VER(12, 74))) {
272+
pg_enable = intel_uncore_read(uncore, GEN9_PG_ENABLE);
273+
if (pg_enable & GEN9_RENDER_PG_ENABLE)
274+
intel_uncore_write_fw(uncore, GEN9_PG_ENABLE,
275+
pg_enable & ~GEN9_RENDER_PG_ENABLE);
276+
}
277+
}
278+
261279
__wait_gsc_proxy_completed(i915);
262280
__wait_gsc_huc_load_completed(i915);
263281

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