Skip to content

Commit 9b6e63a

Browse files
bijudasgeertu
bijudas
authored and
geertu
committed
clk: renesas: rzv2h: Add MSTOP support
Add MSTOP support to control buses for the individual units on RZ/V2H. Use per-bit (instead of group-based) configuration and atomic counters, to ensure precise control over individual MSTOP bits, and to prevent issues with shared dependencies between module clocks. Co-developed-by: Biju Das <biju.das.jz@bp.renesas.com> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Co-developed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20241213123550.289193-2-biju.das.jz@bp.renesas.com Link: https://lore.kernel.org/20250102181839.352599-2-prabhakar.mahadev-lad.rj@bp.renesas.com Link: https://lore.kernel.org/20250102181839.352599-3-prabhakar.mahadev-lad.rj@bp.renesas.com Link: https://lore.kernel.org/20250102181839.352599-4-prabhakar.mahadev-lad.rj@bp.renesas.com Link: https://lore.kernel.org/20250102181839.352599-5-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
1 parent f962745 commit 9b6e63a

File tree

3 files changed

+252
-79
lines changed

3 files changed

+252
-79
lines changed

‎drivers/clk/renesas/r9a09g057-cpg.c

Lines changed: 104 additions & 51 deletions
Original file line numberDiff line numberDiff line change
@@ -115,57 +115,108 @@ static const struct cpg_core_clk r9a09g057_core_clks[] __initconst = {
115115
};
116116

117117
static const struct rzv2h_mod_clk r9a09g057_mod_clks[] __initconst = {
118-
DEF_MOD_CRITICAL("icu_0_pclk_i", CLK_PLLCM33_DIV16, 0, 5, 0, 5),
119-
DEF_MOD("gtm_0_pclk", CLK_PLLCM33_DIV16, 4, 3, 2, 3),
120-
DEF_MOD("gtm_1_pclk", CLK_PLLCM33_DIV16, 4, 4, 2, 4),
121-
DEF_MOD("gtm_2_pclk", CLK_PLLCLN_DIV16, 4, 5, 2, 5),
122-
DEF_MOD("gtm_3_pclk", CLK_PLLCLN_DIV16, 4, 6, 2, 6),
123-
DEF_MOD("gtm_4_pclk", CLK_PLLCLN_DIV16, 4, 7, 2, 7),
124-
DEF_MOD("gtm_5_pclk", CLK_PLLCLN_DIV16, 4, 8, 2, 8),
125-
DEF_MOD("gtm_6_pclk", CLK_PLLCLN_DIV16, 4, 9, 2, 9),
126-
DEF_MOD("gtm_7_pclk", CLK_PLLCLN_DIV16, 4, 10, 2, 10),
127-
DEF_MOD("wdt_0_clkp", CLK_PLLCM33_DIV16, 4, 11, 2, 11),
128-
DEF_MOD("wdt_0_clk_loco", CLK_QEXTAL, 4, 12, 2, 12),
129-
DEF_MOD("wdt_1_clkp", CLK_PLLCLN_DIV16, 4, 13, 2, 13),
130-
DEF_MOD("wdt_1_clk_loco", CLK_QEXTAL, 4, 14, 2, 14),
131-
DEF_MOD("wdt_2_clkp", CLK_PLLCLN_DIV16, 4, 15, 2, 15),
132-
DEF_MOD("wdt_2_clk_loco", CLK_QEXTAL, 5, 0, 2, 16),
133-
DEF_MOD("wdt_3_clkp", CLK_PLLCLN_DIV16, 5, 1, 2, 17),
134-
DEF_MOD("wdt_3_clk_loco", CLK_QEXTAL, 5, 2, 2, 18),
135-
DEF_MOD("scif_0_clk_pck", CLK_PLLCM33_DIV16, 8, 15, 4, 15),
136-
DEF_MOD("riic_8_ckm", CLK_PLLCM33_DIV16, 9, 3, 4, 19),
137-
DEF_MOD("riic_0_ckm", CLK_PLLCLN_DIV16, 9, 4, 4, 20),
138-
DEF_MOD("riic_1_ckm", CLK_PLLCLN_DIV16, 9, 5, 4, 21),
139-
DEF_MOD("riic_2_ckm", CLK_PLLCLN_DIV16, 9, 6, 4, 22),
140-
DEF_MOD("riic_3_ckm", CLK_PLLCLN_DIV16, 9, 7, 4, 23),
141-
DEF_MOD("riic_4_ckm", CLK_PLLCLN_DIV16, 9, 8, 4, 24),
142-
DEF_MOD("riic_5_ckm", CLK_PLLCLN_DIV16, 9, 9, 4, 25),
143-
DEF_MOD("riic_6_ckm", CLK_PLLCLN_DIV16, 9, 10, 4, 26),
144-
DEF_MOD("riic_7_ckm", CLK_PLLCLN_DIV16, 9, 11, 4, 27),
145-
DEF_MOD("sdhi_0_imclk", CLK_PLLCLN_DIV8, 10, 3, 5, 3),
146-
DEF_MOD("sdhi_0_imclk2", CLK_PLLCLN_DIV8, 10, 4, 5, 4),
147-
DEF_MOD("sdhi_0_clk_hs", CLK_PLLCLN_DIV2, 10, 5, 5, 5),
148-
DEF_MOD("sdhi_0_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 6, 5, 6),
149-
DEF_MOD("sdhi_1_imclk", CLK_PLLCLN_DIV8, 10, 7, 5, 7),
150-
DEF_MOD("sdhi_1_imclk2", CLK_PLLCLN_DIV8, 10, 8, 5, 8),
151-
DEF_MOD("sdhi_1_clk_hs", CLK_PLLCLN_DIV2, 10, 9, 5, 9),
152-
DEF_MOD("sdhi_1_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 10, 5, 10),
153-
DEF_MOD("sdhi_2_imclk", CLK_PLLCLN_DIV8, 10, 11, 5, 11),
154-
DEF_MOD("sdhi_2_imclk2", CLK_PLLCLN_DIV8, 10, 12, 5, 12),
155-
DEF_MOD("sdhi_2_clk_hs", CLK_PLLCLN_DIV2, 10, 13, 5, 13),
156-
DEF_MOD("sdhi_2_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 14, 5, 14),
157-
DEF_MOD("cru_0_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 2, 6, 18),
158-
DEF_MOD_NO_PM("cru_0_vclk", CLK_PLLVDO_CRU0, 13, 3, 6, 19),
159-
DEF_MOD("cru_0_pclk", CLK_PLLDTY_DIV16, 13, 4, 6, 20),
160-
DEF_MOD("cru_1_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 5, 6, 21),
161-
DEF_MOD_NO_PM("cru_1_vclk", CLK_PLLVDO_CRU1, 13, 6, 6, 22),
162-
DEF_MOD("cru_1_pclk", CLK_PLLDTY_DIV16, 13, 7, 6, 23),
163-
DEF_MOD("cru_2_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 8, 6, 24),
164-
DEF_MOD_NO_PM("cru_2_vclk", CLK_PLLVDO_CRU2, 13, 9, 6, 25),
165-
DEF_MOD("cru_2_pclk", CLK_PLLDTY_DIV16, 13, 10, 6, 26),
166-
DEF_MOD("cru_3_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 11, 6, 27),
167-
DEF_MOD_NO_PM("cru_3_vclk", CLK_PLLVDO_CRU3, 13, 12, 6, 28),
168-
DEF_MOD("cru_3_pclk", CLK_PLLDTY_DIV16, 13, 13, 6, 29),
118+
DEF_MOD_CRITICAL("icu_0_pclk_i", CLK_PLLCM33_DIV16, 0, 5, 0, 5,
119+
BUS_MSTOP_NONE),
120+
DEF_MOD("gtm_0_pclk", CLK_PLLCM33_DIV16, 4, 3, 2, 3,
121+
BUS_MSTOP(5, BIT(10))),
122+
DEF_MOD("gtm_1_pclk", CLK_PLLCM33_DIV16, 4, 4, 2, 4,
123+
BUS_MSTOP(5, BIT(11))),
124+
DEF_MOD("gtm_2_pclk", CLK_PLLCLN_DIV16, 4, 5, 2, 5,
125+
BUS_MSTOP(2, BIT(13))),
126+
DEF_MOD("gtm_3_pclk", CLK_PLLCLN_DIV16, 4, 6, 2, 6,
127+
BUS_MSTOP(2, BIT(14))),
128+
DEF_MOD("gtm_4_pclk", CLK_PLLCLN_DIV16, 4, 7, 2, 7,
129+
BUS_MSTOP(11, BIT(13))),
130+
DEF_MOD("gtm_5_pclk", CLK_PLLCLN_DIV16, 4, 8, 2, 8,
131+
BUS_MSTOP(11, BIT(14))),
132+
DEF_MOD("gtm_6_pclk", CLK_PLLCLN_DIV16, 4, 9, 2, 9,
133+
BUS_MSTOP(11, BIT(15))),
134+
DEF_MOD("gtm_7_pclk", CLK_PLLCLN_DIV16, 4, 10, 2, 10,
135+
BUS_MSTOP(12, BIT(0))),
136+
DEF_MOD("wdt_0_clkp", CLK_PLLCM33_DIV16, 4, 11, 2, 11,
137+
BUS_MSTOP(3, BIT(10))),
138+
DEF_MOD("wdt_0_clk_loco", CLK_QEXTAL, 4, 12, 2, 12,
139+
BUS_MSTOP(3, BIT(10))),
140+
DEF_MOD("wdt_1_clkp", CLK_PLLCLN_DIV16, 4, 13, 2, 13,
141+
BUS_MSTOP(1, BIT(0))),
142+
DEF_MOD("wdt_1_clk_loco", CLK_QEXTAL, 4, 14, 2, 14,
143+
BUS_MSTOP(1, BIT(0))),
144+
DEF_MOD("wdt_2_clkp", CLK_PLLCLN_DIV16, 4, 15, 2, 15,
145+
BUS_MSTOP(5, BIT(12))),
146+
DEF_MOD("wdt_2_clk_loco", CLK_QEXTAL, 5, 0, 2, 16,
147+
BUS_MSTOP(5, BIT(12))),
148+
DEF_MOD("wdt_3_clkp", CLK_PLLCLN_DIV16, 5, 1, 2, 17,
149+
BUS_MSTOP(5, BIT(13))),
150+
DEF_MOD("wdt_3_clk_loco", CLK_QEXTAL, 5, 2, 2, 18,
151+
BUS_MSTOP(5, BIT(13))),
152+
DEF_MOD("scif_0_clk_pck", CLK_PLLCM33_DIV16, 8, 15, 4, 15,
153+
BUS_MSTOP(3, BIT(14))),
154+
DEF_MOD("riic_8_ckm", CLK_PLLCM33_DIV16, 9, 3, 4, 19,
155+
BUS_MSTOP(3, BIT(13))),
156+
DEF_MOD("riic_0_ckm", CLK_PLLCLN_DIV16, 9, 4, 4, 20,
157+
BUS_MSTOP(1, BIT(1))),
158+
DEF_MOD("riic_1_ckm", CLK_PLLCLN_DIV16, 9, 5, 4, 21,
159+
BUS_MSTOP(1, BIT(2))),
160+
DEF_MOD("riic_2_ckm", CLK_PLLCLN_DIV16, 9, 6, 4, 22,
161+
BUS_MSTOP(1, BIT(3))),
162+
DEF_MOD("riic_3_ckm", CLK_PLLCLN_DIV16, 9, 7, 4, 23,
163+
BUS_MSTOP(1, BIT(4))),
164+
DEF_MOD("riic_4_ckm", CLK_PLLCLN_DIV16, 9, 8, 4, 24,
165+
BUS_MSTOP(1, BIT(5))),
166+
DEF_MOD("riic_5_ckm", CLK_PLLCLN_DIV16, 9, 9, 4, 25,
167+
BUS_MSTOP(1, BIT(6))),
168+
DEF_MOD("riic_6_ckm", CLK_PLLCLN_DIV16, 9, 10, 4, 26,
169+
BUS_MSTOP(1, BIT(7))),
170+
DEF_MOD("riic_7_ckm", CLK_PLLCLN_DIV16, 9, 11, 4, 27,
171+
BUS_MSTOP(1, BIT(8))),
172+
DEF_MOD("sdhi_0_imclk", CLK_PLLCLN_DIV8, 10, 3, 5, 3,
173+
BUS_MSTOP(8, BIT(2))),
174+
DEF_MOD("sdhi_0_imclk2", CLK_PLLCLN_DIV8, 10, 4, 5, 4,
175+
BUS_MSTOP(8, BIT(2))),
176+
DEF_MOD("sdhi_0_clk_hs", CLK_PLLCLN_DIV2, 10, 5, 5, 5,
177+
BUS_MSTOP(8, BIT(2))),
178+
DEF_MOD("sdhi_0_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 6, 5, 6,
179+
BUS_MSTOP(8, BIT(2))),
180+
DEF_MOD("sdhi_1_imclk", CLK_PLLCLN_DIV8, 10, 7, 5, 7,
181+
BUS_MSTOP(8, BIT(3))),
182+
DEF_MOD("sdhi_1_imclk2", CLK_PLLCLN_DIV8, 10, 8, 5, 8,
183+
BUS_MSTOP(8, BIT(3))),
184+
DEF_MOD("sdhi_1_clk_hs", CLK_PLLCLN_DIV2, 10, 9, 5, 9,
185+
BUS_MSTOP(8, BIT(3))),
186+
DEF_MOD("sdhi_1_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 10, 5, 10,
187+
BUS_MSTOP(8, BIT(3))),
188+
DEF_MOD("sdhi_2_imclk", CLK_PLLCLN_DIV8, 10, 11, 5, 11,
189+
BUS_MSTOP(8, BIT(4))),
190+
DEF_MOD("sdhi_2_imclk2", CLK_PLLCLN_DIV8, 10, 12, 5, 12,
191+
BUS_MSTOP(8, BIT(4))),
192+
DEF_MOD("sdhi_2_clk_hs", CLK_PLLCLN_DIV2, 10, 13, 5, 13,
193+
BUS_MSTOP(8, BIT(4))),
194+
DEF_MOD("sdhi_2_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 14, 5, 14,
195+
BUS_MSTOP(8, BIT(4))),
196+
DEF_MOD("cru_0_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 2, 6, 18,
197+
BUS_MSTOP(9, BIT(4))),
198+
DEF_MOD_NO_PM("cru_0_vclk", CLK_PLLVDO_CRU0, 13, 3, 6, 19,
199+
BUS_MSTOP(9, BIT(4))),
200+
DEF_MOD("cru_0_pclk", CLK_PLLDTY_DIV16, 13, 4, 6, 20,
201+
BUS_MSTOP(9, BIT(4))),
202+
DEF_MOD("cru_1_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 5, 6, 21,
203+
BUS_MSTOP(9, BIT(5))),
204+
DEF_MOD_NO_PM("cru_1_vclk", CLK_PLLVDO_CRU1, 13, 6, 6, 22,
205+
BUS_MSTOP(9, BIT(5))),
206+
DEF_MOD("cru_1_pclk", CLK_PLLDTY_DIV16, 13, 7, 6, 23,
207+
BUS_MSTOP(9, BIT(5))),
208+
DEF_MOD("cru_2_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 8, 6, 24,
209+
BUS_MSTOP(9, BIT(6))),
210+
DEF_MOD_NO_PM("cru_2_vclk", CLK_PLLVDO_CRU2, 13, 9, 6, 25,
211+
BUS_MSTOP(9, BIT(6))),
212+
DEF_MOD("cru_2_pclk", CLK_PLLDTY_DIV16, 13, 10, 6, 26,
213+
BUS_MSTOP(9, BIT(6))),
214+
DEF_MOD("cru_3_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 11, 6, 27,
215+
BUS_MSTOP(9, BIT(7))),
216+
DEF_MOD_NO_PM("cru_3_vclk", CLK_PLLVDO_CRU3, 13, 12, 6, 28,
217+
BUS_MSTOP(9, BIT(7))),
218+
DEF_MOD("cru_3_pclk", CLK_PLLDTY_DIV16, 13, 13, 6, 29,
219+
BUS_MSTOP(9, BIT(7))),
169220
};
170221

171222
static const struct rzv2h_reset r9a09g057_resets[] __initconst = {
@@ -224,4 +275,6 @@ const struct rzv2h_cpg_info r9a09g057_cpg_info __initconst = {
224275
/* Resets */
225276
.resets = r9a09g057_resets,
226277
.num_resets = ARRAY_SIZE(r9a09g057_resets),
278+
279+
.num_mstop_bits = 192,
227280
};

0 commit comments

Comments
 (0)