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airliedairlied
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Merge tag 'drm-intel-fixes-2025-04-09' of https://gitlab.freedesktop.org/drm/i915/kernel into drm-fixes
drm/i915 fixes for v6.15-rc2: - Fix scanline offset for LNL+ and BMG+ - Fix GVT unterminated-string-initialization build warning - Fix DP rate limit when sink doesn't support TPS4 - Handle GDDR + ECC memory type detection - Fix VRR parameter change check - Fix fence not released on early probe errors - Disable render power gating during live selftests Signed-off-by: Dave Airlie <airlied@redhat.com> From: Jani Nikula <jani.nikula@intel.com> Link: https://lore.kernel.org/r/87lds9wlpq.fsf@intel.com
2 parents 0af2f6b + e3ea2ea commit 9afaa16

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13 files changed

+100
-34
lines changed

13 files changed

+100
-34
lines changed

‎drivers/gpu/drm/i915/display/intel_bw.c

Lines changed: 13 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -244,6 +244,7 @@ static int icl_get_qgv_points(struct drm_i915_private *dev_priv,
244244
qi->deinterleave = 4;
245245
break;
246246
case INTEL_DRAM_GDDR:
247+
case INTEL_DRAM_GDDR_ECC:
247248
qi->channel_width = 32;
248249
break;
249250
default:
@@ -398,6 +399,12 @@ static const struct intel_sa_info xe2_hpd_sa_info = {
398399
/* Other values not used by simplified algorithm */
399400
};
400401

402+
static const struct intel_sa_info xe2_hpd_ecc_sa_info = {
403+
.derating = 45,
404+
.deprogbwlimit = 53,
405+
/* Other values not used by simplified algorithm */
406+
};
407+
401408
static int icl_get_bw_info(struct drm_i915_private *dev_priv, const struct intel_sa_info *sa)
402409
{
403410
struct intel_qgv_info qi = {};
@@ -740,10 +747,15 @@ static unsigned int icl_qgv_bw(struct drm_i915_private *i915,
740747

741748
void intel_bw_init_hw(struct drm_i915_private *dev_priv)
742749
{
750+
const struct dram_info *dram_info = &dev_priv->dram_info;
751+
743752
if (!HAS_DISPLAY(dev_priv))
744753
return;
745754

746-
if (DISPLAY_VERx100(dev_priv) >= 1401 && IS_DGFX(dev_priv))
755+
if (DISPLAY_VERx100(dev_priv) >= 1401 && IS_DGFX(dev_priv) &&
756+
dram_info->type == INTEL_DRAM_GDDR_ECC)
757+
xe2_hpd_get_bw_info(dev_priv, &xe2_hpd_ecc_sa_info);
758+
else if (DISPLAY_VERx100(dev_priv) >= 1401 && IS_DGFX(dev_priv))
747759
xe2_hpd_get_bw_info(dev_priv, &xe2_hpd_sa_info);
748760
else if (DISPLAY_VER(dev_priv) >= 14)
749761
tgl_get_bw_info(dev_priv, &mtl_sa_info);

‎drivers/gpu/drm/i915/display/intel_display.c

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -968,7 +968,9 @@ static bool vrr_params_changed(const struct intel_crtc_state *old_crtc_state,
968968
old_crtc_state->vrr.vmin != new_crtc_state->vrr.vmin ||
969969
old_crtc_state->vrr.vmax != new_crtc_state->vrr.vmax ||
970970
old_crtc_state->vrr.guardband != new_crtc_state->vrr.guardband ||
971-
old_crtc_state->vrr.pipeline_full != new_crtc_state->vrr.pipeline_full;
971+
old_crtc_state->vrr.pipeline_full != new_crtc_state->vrr.pipeline_full ||
972+
old_crtc_state->vrr.vsync_start != new_crtc_state->vrr.vsync_start ||
973+
old_crtc_state->vrr.vsync_end != new_crtc_state->vrr.vsync_end;
972974
}
973975

974976
static bool cmrr_params_changed(const struct intel_crtc_state *old_crtc_state,

‎drivers/gpu/drm/i915/display/intel_dp.c

Lines changed: 42 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -172,10 +172,28 @@ int intel_dp_link_symbol_clock(int rate)
172172

173173
static int max_dprx_rate(struct intel_dp *intel_dp)
174174
{
175+
struct intel_display *display = to_intel_display(intel_dp);
176+
struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
177+
int max_rate;
178+
175179
if (intel_dp_tunnel_bw_alloc_is_enabled(intel_dp))
176-
return drm_dp_tunnel_max_dprx_rate(intel_dp->tunnel);
180+
max_rate = drm_dp_tunnel_max_dprx_rate(intel_dp->tunnel);
181+
else
182+
max_rate = drm_dp_bw_code_to_link_rate(intel_dp->dpcd[DP_MAX_LINK_RATE]);
177183

178-
return drm_dp_bw_code_to_link_rate(intel_dp->dpcd[DP_MAX_LINK_RATE]);
184+
/*
185+
* Some broken eDP sinks illegally declare support for
186+
* HBR3 without TPS4, and are unable to produce a stable
187+
* output. Reject HBR3 when TPS4 is not available.
188+
*/
189+
if (max_rate >= 810000 && !drm_dp_tps4_supported(intel_dp->dpcd)) {
190+
drm_dbg_kms(display->drm,
191+
"[ENCODER:%d:%s] Rejecting HBR3 due to missing TPS4 support\n",
192+
encoder->base.base.id, encoder->base.name);
193+
max_rate = 540000;
194+
}
195+
196+
return max_rate;
179197
}
180198

181199
static int max_dprx_lane_count(struct intel_dp *intel_dp)
@@ -4170,6 +4188,9 @@ static void intel_edp_mso_init(struct intel_dp *intel_dp)
41704188
static void
41714189
intel_edp_set_sink_rates(struct intel_dp *intel_dp)
41724190
{
4191+
struct intel_display *display = to_intel_display(intel_dp);
4192+
struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
4193+
41734194
intel_dp->num_sink_rates = 0;
41744195

41754196
if (intel_dp->edp_dpcd[0] >= DP_EDP_14) {
@@ -4180,18 +4201,32 @@ intel_edp_set_sink_rates(struct intel_dp *intel_dp)
41804201
sink_rates, sizeof(sink_rates));
41814202

41824203
for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
4183-
int val = le16_to_cpu(sink_rates[i]);
4184-
4185-
if (val == 0)
4186-
break;
4204+
int rate;
41874205

41884206
/* Value read multiplied by 200kHz gives the per-lane
41894207
* link rate in kHz. The source rates are, however,
41904208
* stored in terms of LS_Clk kHz. The full conversion
41914209
* back to symbols is
41924210
* (val * 200kHz)*(8/10 ch. encoding)*(1/8 bit to Byte)
41934211
*/
4194-
intel_dp->sink_rates[i] = (val * 200) / 10;
4212+
rate = le16_to_cpu(sink_rates[i]) * 200 / 10;
4213+
4214+
if (rate == 0)
4215+
break;
4216+
4217+
/*
4218+
* Some broken eDP sinks illegally declare support for
4219+
* HBR3 without TPS4, and are unable to produce a stable
4220+
* output. Reject HBR3 when TPS4 is not available.
4221+
*/
4222+
if (rate >= 810000 && !drm_dp_tps4_supported(intel_dp->dpcd)) {
4223+
drm_dbg_kms(display->drm,
4224+
"[ENCODER:%d:%s] Rejecting HBR3 due to missing TPS4 support\n",
4225+
encoder->base.base.id, encoder->base.name);
4226+
break;
4227+
}
4228+
4229+
intel_dp->sink_rates[i] = rate;
41954230
}
41964231
intel_dp->num_sink_rates = i;
41974232
}

‎drivers/gpu/drm/i915/display/intel_vblank.c

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -222,7 +222,9 @@ int intel_crtc_scanline_offset(const struct intel_crtc_state *crtc_state)
222222
* However if queried just before the start of vblank we'll get an
223223
* answer that's slightly in the future.
224224
*/
225-
if (DISPLAY_VER(display) == 2)
225+
if (DISPLAY_VER(display) >= 20 || display->platform.battlemage)
226+
return 1;
227+
else if (DISPLAY_VER(display) == 2)
226228
return -1;
227229
else if (HAS_DDI(display) && intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
228230
return 2;

‎drivers/gpu/drm/i915/gt/intel_rc6.c

Lines changed: 4 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -117,21 +117,10 @@ static void gen11_rc6_enable(struct intel_rc6 *rc6)
117117
GEN6_RC_CTL_RC6_ENABLE |
118118
GEN6_RC_CTL_EI_MODE(1);
119119

120-
/*
121-
* BSpec 52698 - Render powergating must be off.
122-
* FIXME BSpec is outdated, disabling powergating for MTL is just
123-
* temporary wa and should be removed after fixing real cause
124-
* of forcewake timeouts.
125-
*/
126-
if (IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 74)))
127-
pg_enable =
128-
GEN9_MEDIA_PG_ENABLE |
129-
GEN11_MEDIA_SAMPLER_PG_ENABLE;
130-
else
131-
pg_enable =
132-
GEN9_RENDER_PG_ENABLE |
133-
GEN9_MEDIA_PG_ENABLE |
134-
GEN11_MEDIA_SAMPLER_PG_ENABLE;
120+
pg_enable =
121+
GEN9_RENDER_PG_ENABLE |
122+
GEN9_MEDIA_PG_ENABLE |
123+
GEN11_MEDIA_SAMPLER_PG_ENABLE;
135124

136125
if (GRAPHICS_VER(gt->i915) >= 12 && !IS_DG1(gt->i915)) {
137126
for (i = 0; i < I915_MAX_VCS; i++)

‎drivers/gpu/drm/i915/gt/uc/intel_huc.c

Lines changed: 5 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -317,6 +317,11 @@ void intel_huc_init_early(struct intel_huc *huc)
317317
}
318318
}
319319

320+
void intel_huc_fini_late(struct intel_huc *huc)
321+
{
322+
delayed_huc_load_fini(huc);
323+
}
324+
320325
#define HUC_LOAD_MODE_STRING(x) (x ? "GSC" : "legacy")
321326
static int check_huc_loading_mode(struct intel_huc *huc)
322327
{
@@ -414,12 +419,6 @@ int intel_huc_init(struct intel_huc *huc)
414419

415420
void intel_huc_fini(struct intel_huc *huc)
416421
{
417-
/*
418-
* the fence is initialized in init_early, so we need to clean it up
419-
* even if HuC loading is off.
420-
*/
421-
delayed_huc_load_fini(huc);
422-
423422
if (huc->heci_pkt)
424423
i915_vma_unpin_and_release(&huc->heci_pkt, 0);
425424

‎drivers/gpu/drm/i915/gt/uc/intel_huc.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -55,6 +55,7 @@ struct intel_huc {
5555

5656
int intel_huc_sanitize(struct intel_huc *huc);
5757
void intel_huc_init_early(struct intel_huc *huc);
58+
void intel_huc_fini_late(struct intel_huc *huc);
5859
int intel_huc_init(struct intel_huc *huc);
5960
void intel_huc_fini(struct intel_huc *huc);
6061
int intel_huc_auth(struct intel_huc *huc, enum intel_huc_authentication_type type);

‎drivers/gpu/drm/i915/gt/uc/intel_uc.c

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -136,6 +136,7 @@ void intel_uc_init_late(struct intel_uc *uc)
136136

137137
void intel_uc_driver_late_release(struct intel_uc *uc)
138138
{
139+
intel_huc_fini_late(&uc->huc);
139140
}
140141

141142
/**

‎drivers/gpu/drm/i915/gvt/opregion.c

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -222,7 +222,6 @@ int intel_vgpu_init_opregion(struct intel_vgpu *vgpu)
222222
u8 *buf;
223223
struct opregion_header *header;
224224
struct vbt v;
225-
const char opregion_signature[16] = OPREGION_SIGNATURE;
226225

227226
gvt_dbg_core("init vgpu%d opregion\n", vgpu->id);
228227
vgpu_opregion(vgpu)->va = (void *)__get_free_pages(GFP_KERNEL |
@@ -236,8 +235,10 @@ int intel_vgpu_init_opregion(struct intel_vgpu *vgpu)
236235
/* emulated opregion with VBT mailbox only */
237236
buf = (u8 *)vgpu_opregion(vgpu)->va;
238237
header = (struct opregion_header *)buf;
239-
memcpy(header->signature, opregion_signature,
240-
sizeof(opregion_signature));
238+
239+
static_assert(sizeof(header->signature) == sizeof(OPREGION_SIGNATURE) - 1);
240+
memcpy(header->signature, OPREGION_SIGNATURE, sizeof(header->signature));
241+
241242
header->size = 0x8;
242243
header->opregion_ver = 0x02000000;
243244
header->mboxes = MBOX_VBT;

‎drivers/gpu/drm/i915/i915_drv.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -305,6 +305,7 @@ struct drm_i915_private {
305305
INTEL_DRAM_DDR5,
306306
INTEL_DRAM_LPDDR5,
307307
INTEL_DRAM_GDDR,
308+
INTEL_DRAM_GDDR_ECC,
308309
} type;
309310
u8 num_qgv_points;
310311
u8 num_psf_gv_points;

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