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LoongArch: Add SCHED_MC (Multi-core scheduler) support
In order to achieve more reasonable load balancing behavior, add SCHED_MC (Multi-core scheduler) support. The LLC distribution of LoongArch now is consistent with NUMA node, the balancing domain of SCHED_MC can effectively reduce the situation where processes are awakened to smt_sibling. Co-developed-by: Hongliang Wang <wanghongliang@loongson.cn> Signed-off-by: Hongliang Wang <wanghongliang@loongson.cn> Signed-off-by: Tianyang Zhang <zhangtianyang@loongson.cn> Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
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arch/loongarch/Kconfig

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@@ -456,6 +456,15 @@ config SCHED_SMT
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Improves scheduler's performance when there are multiple
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threads in one physical core.
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config SCHED_MC
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bool "Multi-core scheduler support"
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depends on SMP
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default y
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help
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Multi-core scheduler support improves the CPU scheduler's decision
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making when dealing with multi-core CPU chips at a cost of slightly
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increased overhead in some places.
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config SMP
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bool "Multi-Processing support"
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help

arch/loongarch/include/asm/smp.h

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@@ -25,6 +25,7 @@ extern int smp_num_siblings;
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extern int num_processors;
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extern int disabled_cpus;
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extern cpumask_t cpu_sibling_map[];
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extern cpumask_t cpu_llc_shared_map[];
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extern cpumask_t cpu_core_map[];
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extern cpumask_t cpu_foreign_map[];
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arch/loongarch/include/asm/topology.h

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@@ -30,6 +30,14 @@ void numa_set_distance(int from, int to, int distance);
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#endif
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#ifdef CONFIG_SMP
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/*
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* Return cpus that shares the last level cache.
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*/
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static inline const struct cpumask *cpu_coregroup_mask(int cpu)
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{
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return &cpu_llc_shared_map[cpu];
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}
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#define topology_physical_package_id(cpu) (cpu_data[cpu].package)
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#define topology_core_id(cpu) (cpu_data[cpu].core)
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#define topology_core_cpumask(cpu) (&cpu_core_map[cpu])

arch/loongarch/kernel/smp.c

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@@ -46,6 +46,10 @@ EXPORT_SYMBOL(__cpu_logical_map);
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cpumask_t cpu_sibling_map[NR_CPUS] __read_mostly;
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EXPORT_SYMBOL(cpu_sibling_map);
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/* Representing the last level cache shared map of each logical CPU */
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cpumask_t cpu_llc_shared_map[NR_CPUS] __read_mostly;
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EXPORT_SYMBOL(cpu_llc_shared_map);
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/* Representing the core map of multi-core chips of each logical CPU */
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cpumask_t cpu_core_map[NR_CPUS] __read_mostly;
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EXPORT_SYMBOL(cpu_core_map);
@@ -63,6 +67,9 @@ EXPORT_SYMBOL(cpu_foreign_map);
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/* representing cpus for which sibling maps can be computed */
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static cpumask_t cpu_sibling_setup_map;
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/* representing cpus for which llc shared maps can be computed */
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static cpumask_t cpu_llc_shared_setup_map;
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/* representing cpus for which core maps can be computed */
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static cpumask_t cpu_core_setup_map;
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@@ -102,6 +109,34 @@ static inline void set_cpu_core_map(int cpu)
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}
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}
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static inline void set_cpu_llc_shared_map(int cpu)
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{
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int i;
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cpumask_set_cpu(cpu, &cpu_llc_shared_setup_map);
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for_each_cpu(i, &cpu_llc_shared_setup_map) {
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if (cpu_to_node(cpu) == cpu_to_node(i)) {
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cpumask_set_cpu(i, &cpu_llc_shared_map[cpu]);
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cpumask_set_cpu(cpu, &cpu_llc_shared_map[i]);
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}
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}
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}
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static inline void clear_cpu_llc_shared_map(int cpu)
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{
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int i;
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for_each_cpu(i, &cpu_llc_shared_setup_map) {
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if (cpu_to_node(cpu) == cpu_to_node(i)) {
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cpumask_clear_cpu(i, &cpu_llc_shared_map[cpu]);
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cpumask_clear_cpu(cpu, &cpu_llc_shared_map[i]);
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}
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}
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cpumask_clear_cpu(cpu, &cpu_llc_shared_setup_map);
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}
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static inline void set_cpu_sibling_map(int cpu)
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{
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int i;
@@ -406,6 +441,7 @@ int loongson_cpu_disable(void)
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#endif
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set_cpu_online(cpu, false);
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clear_cpu_sibling_map(cpu);
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clear_cpu_llc_shared_map(cpu);
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calculate_cpu_foreign_map();
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local_irq_save(flags);
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irq_migrate_all_off_this_cpu();
@@ -572,6 +608,7 @@ void __init smp_prepare_cpus(unsigned int max_cpus)
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current_thread_info()->cpu = 0;
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loongson_prepare_cpus(max_cpus);
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set_cpu_sibling_map(0);
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set_cpu_llc_shared_map(0);
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set_cpu_core_map(0);
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calculate_cpu_foreign_map();
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#ifndef CONFIG_HOTPLUG_CPU
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loongson_init_secondary();
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set_cpu_sibling_map(cpu);
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set_cpu_llc_shared_map(cpu);
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set_cpu_core_map(cpu);
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notify_cpu_starting(cpu);

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