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ASoC: mediatek: mt8183-afe-pcm: Shorten memif_data table using macros
The memif_data table describes all the supported PCM channels for the audio frontend. Most of the fields are either the same or can be derived from the interface's name. This results in a very long table (in source code) that can be shortened with macros. Do just that. Some "convenience" macros were added to cover non-existent register fields that would otherwise require multiple layers of macros to handle. Signed-off-by: Chen-Yu Tsai <wenst@chromium.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://patch.msgid.link/20250515073825.4155297-2-wenst@chromium.org Signed-off-by: Mark Brown <broonie@kernel.org>
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‎sound/soc/mediatek/mt8183/mt8183-afe-pcm.c

Lines changed: 54 additions & 189 deletions
Original file line numberDiff line numberDiff line change
@@ -424,196 +424,61 @@ static const struct snd_soc_component_driver mt8183_afe_pcm_dai_component = {
424424
.name = "mt8183-afe-pcm-dai",
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};
426426

427+
#define MT8183_MEMIF_BASE(_id, _en_reg, _fs_reg, _mono_reg) \
428+
[MT8183_MEMIF_##_id] = { \
429+
.name = #_id, \
430+
.id = MT8183_MEMIF_##_id, \
431+
.reg_ofs_base = AFE_##_id##_BASE, \
432+
.reg_ofs_cur = AFE_##_id##_CUR, \
433+
.reg_ofs_end = AFE_##_id##_END, \
434+
.fs_reg = (_fs_reg), \
435+
.fs_shift = _id##_MODE_SFT, \
436+
.fs_maskbit = _id##_MODE_MASK, \
437+
.mono_reg = (_mono_reg), \
438+
.mono_shift = _id##_DATA_SFT, \
439+
.enable_reg = (_en_reg), \
440+
.enable_shift = _id##_ON_SFT, \
441+
.hd_reg = AFE_MEMIF_HD_MODE, \
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.hd_align_reg = AFE_MEMIF_HDALIGN, \
443+
.hd_shift = _id##_HD_SFT, \
444+
.hd_align_mshift = _id##_HD_ALIGN_SFT, \
445+
.agent_disable_reg = -1, \
446+
.agent_disable_shift = -1, \
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.msb_reg = -1, \
448+
.msb_shift = -1, \
449+
}
450+
451+
#define MT8183_MEMIF(_id, _fs_reg, _mono_reg) \
452+
MT8183_MEMIF_BASE(_id, AFE_DAC_CON0, _fs_reg, _mono_reg)
453+
454+
/* For convenience with macros: missing register fields */
455+
#define MOD_DAI_DATA_SFT -1
456+
#define HDMI_MODE_SFT -1
457+
#define HDMI_MODE_MASK -1
458+
#define HDMI_DATA_SFT -1
459+
#define HDMI_ON_SFT -1
460+
461+
/* For convenience with macros: register name differences */
462+
#define AFE_VUL12_BASE AFE_VUL_D2_BASE
463+
#define AFE_VUL12_CUR AFE_VUL_D2_CUR
464+
#define AFE_VUL12_END AFE_VUL_D2_END
465+
#define AWB2_HD_ALIGN_SFT AWB2_ALIGN_SFT
466+
#define VUL12_DATA_SFT VUL12_MONO_SFT
467+
#define AFE_HDMI_BASE AFE_HDMI_OUT_BASE
468+
#define AFE_HDMI_CUR AFE_HDMI_OUT_CUR
469+
#define AFE_HDMI_END AFE_HDMI_OUT_END
470+
427471
static const struct mtk_base_memif_data memif_data[MT8183_MEMIF_NUM] = {
428-
[MT8183_MEMIF_DL1] = {
429-
.name = "DL1",
430-
.id = MT8183_MEMIF_DL1,
431-
.reg_ofs_base = AFE_DL1_BASE,
432-
.reg_ofs_cur = AFE_DL1_CUR,
433-
.fs_reg = AFE_DAC_CON1,
434-
.fs_shift = DL1_MODE_SFT,
435-
.fs_maskbit = DL1_MODE_MASK,
436-
.mono_reg = AFE_DAC_CON1,
437-
.mono_shift = DL1_DATA_SFT,
438-
.enable_reg = AFE_DAC_CON0,
439-
.enable_shift = DL1_ON_SFT,
440-
.hd_reg = AFE_MEMIF_HD_MODE,
441-
.hd_align_reg = AFE_MEMIF_HDALIGN,
442-
.hd_shift = DL1_HD_SFT,
443-
.hd_align_mshift = DL1_HD_ALIGN_SFT,
444-
.agent_disable_reg = -1,
445-
.agent_disable_shift = -1,
446-
.msb_reg = -1,
447-
.msb_shift = -1,
448-
},
449-
[MT8183_MEMIF_DL2] = {
450-
.name = "DL2",
451-
.id = MT8183_MEMIF_DL2,
452-
.reg_ofs_base = AFE_DL2_BASE,
453-
.reg_ofs_cur = AFE_DL2_CUR,
454-
.fs_reg = AFE_DAC_CON1,
455-
.fs_shift = DL2_MODE_SFT,
456-
.fs_maskbit = DL2_MODE_MASK,
457-
.mono_reg = AFE_DAC_CON1,
458-
.mono_shift = DL2_DATA_SFT,
459-
.enable_reg = AFE_DAC_CON0,
460-
.enable_shift = DL2_ON_SFT,
461-
.hd_reg = AFE_MEMIF_HD_MODE,
462-
.hd_align_reg = AFE_MEMIF_HDALIGN,
463-
.hd_shift = DL2_HD_SFT,
464-
.hd_align_mshift = DL2_HD_ALIGN_SFT,
465-
.agent_disable_reg = -1,
466-
.agent_disable_shift = -1,
467-
.msb_reg = -1,
468-
.msb_shift = -1,
469-
},
470-
[MT8183_MEMIF_DL3] = {
471-
.name = "DL3",
472-
.id = MT8183_MEMIF_DL3,
473-
.reg_ofs_base = AFE_DL3_BASE,
474-
.reg_ofs_cur = AFE_DL3_CUR,
475-
.fs_reg = AFE_DAC_CON2,
476-
.fs_shift = DL3_MODE_SFT,
477-
.fs_maskbit = DL3_MODE_MASK,
478-
.mono_reg = AFE_DAC_CON1,
479-
.mono_shift = DL3_DATA_SFT,
480-
.enable_reg = AFE_DAC_CON0,
481-
.enable_shift = DL3_ON_SFT,
482-
.hd_reg = AFE_MEMIF_HD_MODE,
483-
.hd_align_reg = AFE_MEMIF_HDALIGN,
484-
.hd_shift = DL3_HD_SFT,
485-
.hd_align_mshift = DL3_HD_ALIGN_SFT,
486-
.agent_disable_reg = -1,
487-
.agent_disable_shift = -1,
488-
.msb_reg = -1,
489-
.msb_shift = -1,
490-
},
491-
[MT8183_MEMIF_VUL2] = {
492-
.name = "VUL2",
493-
.id = MT8183_MEMIF_VUL2,
494-
.reg_ofs_base = AFE_VUL2_BASE,
495-
.reg_ofs_cur = AFE_VUL2_CUR,
496-
.fs_reg = AFE_DAC_CON2,
497-
.fs_shift = VUL2_MODE_SFT,
498-
.fs_maskbit = VUL2_MODE_MASK,
499-
.mono_reg = AFE_DAC_CON2,
500-
.mono_shift = VUL2_DATA_SFT,
501-
.enable_reg = AFE_DAC_CON0,
502-
.enable_shift = VUL2_ON_SFT,
503-
.hd_reg = AFE_MEMIF_HD_MODE,
504-
.hd_align_reg = AFE_MEMIF_HDALIGN,
505-
.hd_shift = VUL2_HD_SFT,
506-
.hd_align_mshift = VUL2_HD_ALIGN_SFT,
507-
.agent_disable_reg = -1,
508-
.agent_disable_shift = -1,
509-
.msb_reg = -1,
510-
.msb_shift = -1,
511-
},
512-
[MT8183_MEMIF_AWB] = {
513-
.name = "AWB",
514-
.id = MT8183_MEMIF_AWB,
515-
.reg_ofs_base = AFE_AWB_BASE,
516-
.reg_ofs_cur = AFE_AWB_CUR,
517-
.fs_reg = AFE_DAC_CON1,
518-
.fs_shift = AWB_MODE_SFT,
519-
.fs_maskbit = AWB_MODE_MASK,
520-
.mono_reg = AFE_DAC_CON1,
521-
.mono_shift = AWB_DATA_SFT,
522-
.enable_reg = AFE_DAC_CON0,
523-
.enable_shift = AWB_ON_SFT,
524-
.hd_reg = AFE_MEMIF_HD_MODE,
525-
.hd_align_reg = AFE_MEMIF_HDALIGN,
526-
.hd_shift = AWB_HD_SFT,
527-
.hd_align_mshift = AWB_HD_ALIGN_SFT,
528-
.agent_disable_reg = -1,
529-
.agent_disable_shift = -1,
530-
.msb_reg = -1,
531-
.msb_shift = -1,
532-
},
533-
[MT8183_MEMIF_AWB2] = {
534-
.name = "AWB2",
535-
.id = MT8183_MEMIF_AWB2,
536-
.reg_ofs_base = AFE_AWB2_BASE,
537-
.reg_ofs_cur = AFE_AWB2_CUR,
538-
.fs_reg = AFE_DAC_CON2,
539-
.fs_shift = AWB2_MODE_SFT,
540-
.fs_maskbit = AWB2_MODE_MASK,
541-
.mono_reg = AFE_DAC_CON2,
542-
.mono_shift = AWB2_DATA_SFT,
543-
.enable_reg = AFE_DAC_CON0,
544-
.enable_shift = AWB2_ON_SFT,
545-
.hd_reg = AFE_MEMIF_HD_MODE,
546-
.hd_align_reg = AFE_MEMIF_HDALIGN,
547-
.hd_shift = AWB2_HD_SFT,
548-
.hd_align_mshift = AWB2_ALIGN_SFT,
549-
.agent_disable_reg = -1,
550-
.agent_disable_shift = -1,
551-
.msb_reg = -1,
552-
.msb_shift = -1,
553-
},
554-
[MT8183_MEMIF_VUL12] = {
555-
.name = "VUL12",
556-
.id = MT8183_MEMIF_VUL12,
557-
.reg_ofs_base = AFE_VUL_D2_BASE,
558-
.reg_ofs_cur = AFE_VUL_D2_CUR,
559-
.fs_reg = AFE_DAC_CON0,
560-
.fs_shift = VUL12_MODE_SFT,
561-
.fs_maskbit = VUL12_MODE_MASK,
562-
.mono_reg = AFE_DAC_CON0,
563-
.mono_shift = VUL12_MONO_SFT,
564-
.enable_reg = AFE_DAC_CON0,
565-
.enable_shift = VUL12_ON_SFT,
566-
.hd_reg = AFE_MEMIF_HD_MODE,
567-
.hd_align_reg = AFE_MEMIF_HDALIGN,
568-
.hd_shift = VUL12_HD_SFT,
569-
.hd_align_mshift = VUL12_HD_ALIGN_SFT,
570-
.agent_disable_reg = -1,
571-
.agent_disable_shift = -1,
572-
.msb_reg = -1,
573-
.msb_shift = -1,
574-
},
575-
[MT8183_MEMIF_MOD_DAI] = {
576-
.name = "MOD_DAI",
577-
.id = MT8183_MEMIF_MOD_DAI,
578-
.reg_ofs_base = AFE_MOD_DAI_BASE,
579-
.reg_ofs_cur = AFE_MOD_DAI_CUR,
580-
.fs_reg = AFE_DAC_CON1,
581-
.fs_shift = MOD_DAI_MODE_SFT,
582-
.fs_maskbit = MOD_DAI_MODE_MASK,
583-
.mono_reg = -1,
584-
.mono_shift = 0,
585-
.enable_reg = AFE_DAC_CON0,
586-
.enable_shift = MOD_DAI_ON_SFT,
587-
.hd_reg = AFE_MEMIF_HD_MODE,
588-
.hd_align_reg = AFE_MEMIF_HDALIGN,
589-
.hd_shift = MOD_DAI_HD_SFT,
590-
.hd_align_mshift = MOD_DAI_HD_ALIGN_SFT,
591-
.agent_disable_reg = -1,
592-
.agent_disable_shift = -1,
593-
.msb_reg = -1,
594-
.msb_shift = -1,
595-
},
596-
[MT8183_MEMIF_HDMI] = {
597-
.name = "HDMI",
598-
.id = MT8183_MEMIF_HDMI,
599-
.reg_ofs_base = AFE_HDMI_OUT_BASE,
600-
.reg_ofs_cur = AFE_HDMI_OUT_CUR,
601-
.fs_reg = -1,
602-
.fs_shift = -1,
603-
.fs_maskbit = -1,
604-
.mono_reg = -1,
605-
.mono_shift = -1,
606-
.enable_reg = -1, /* control in tdm for sync start */
607-
.enable_shift = -1,
608-
.hd_reg = AFE_MEMIF_HD_MODE,
609-
.hd_align_reg = AFE_MEMIF_HDALIGN,
610-
.hd_shift = HDMI_HD_SFT,
611-
.hd_align_mshift = HDMI_HD_ALIGN_SFT,
612-
.agent_disable_reg = -1,
613-
.agent_disable_shift = -1,
614-
.msb_reg = -1,
615-
.msb_shift = -1,
616-
},
472+
MT8183_MEMIF(DL1, AFE_DAC_CON1, AFE_DAC_CON1),
473+
MT8183_MEMIF(DL2, AFE_DAC_CON1, AFE_DAC_CON1),
474+
MT8183_MEMIF(DL3, AFE_DAC_CON2, AFE_DAC_CON1),
475+
MT8183_MEMIF(VUL2, AFE_DAC_CON2, AFE_DAC_CON2),
476+
MT8183_MEMIF(AWB, AFE_DAC_CON1, AFE_DAC_CON1),
477+
MT8183_MEMIF(AWB2, AFE_DAC_CON2, AFE_DAC_CON2),
478+
MT8183_MEMIF(VUL12, AFE_DAC_CON0, AFE_DAC_CON0),
479+
MT8183_MEMIF(MOD_DAI, AFE_DAC_CON1, -1),
480+
/* enable control in tdm for sync start */
481+
MT8183_MEMIF_BASE(HDMI, -1, -1, -1),
617482
};
618483

619484
static const struct mtk_base_irq_data irq_data[MT8183_IRQ_NUM] = {

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