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Merge tag 'mailbox-v6.14' of git://git.kernel.org/pub/scm/linux/kernel/git/jassibrar/mailbox
Pull mailbox updates from Jassi Brar: - samsung: add gs101-mbox driver - microchip: add sbi-ipc driver - zynqmp: fix invalid __percpu annotation - qcom: add IPQ5424 APCS compatible - mpfs fix copy and paste bug - th1520: Fix NULL vs IS_ERR() and a memory corruption bug - tegra-hsp: clear mailbox before using message * tag 'mailbox-v6.14' of git://git.kernel.org/pub/scm/linux/kernel/git/jassibrar/mailbox: riscv: export __cpuid_to_hartid_map riscv: sbi: vendorid_list: Add Microchip Technology to the vendor list mailbox: th1520: Fix memory corruption due to incorrect array size mailbox: zynqmp: Remove invalid __percpu annotation in zynqmp_ipi_probe() MAINTAINERS: add entry for Samsung Exynos mailbox driver mailbox: add Samsung Exynos driver dt-bindings: mailbox: add google,gs101-mbox mailbox: qcom: Add support for IPQ5424 APCS IPC dt-bindings: mailbox: qcom: Add IPQ5424 APCS compatible mailbox: qcom-ipcc: Reset CLEAR_ON_RECV_RD if set from boot firmware mailbox: add Microchip IPC support dt-bindings: mailbox: add binding for Microchip IPC mailbox controller mailbox: tegra-hsp: Clear mailbox before using message mailbox: mpfs: fix copy and paste bug in probe mailbox: th1520: Fix a NULL vs IS_ERR() bug
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‎Documentation/devicetree/bindings/mailbox/google,gs101-mbox.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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# Copyright 2024 Linaro Ltd.
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/mailbox/google,gs101-mbox.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Samsung Exynos Mailbox Controller
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maintainers:
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- Tudor Ambarus <tudor.ambarus@linaro.org>
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description:
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The Samsung Exynos mailbox controller, used on Google GS101 SoC, has 16 flag
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bits for hardware interrupt generation and a shared register for passing
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mailbox messages. When the controller is used by the ACPM interface
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the shared register is ignored and the mailbox controller acts as a doorbell.
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The controller just raises the interrupt to the firmware after the
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ACPM interface has written the message to SRAM.
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properties:
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compatible:
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const: google,gs101-mbox
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reg:
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maxItems: 1
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clocks:
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maxItems: 1
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clock-names:
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items:
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- const: pclk
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interrupts:
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description: IRQ line for the RX mailbox.
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maxItems: 1
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'#mbox-cells':
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const: 0
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- interrupts
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- '#mbox-cells'
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/google,gs101.h>
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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ap2apm_mailbox: mailbox@17610000 {
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compatible = "google,gs101-mbox";
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reg = <0x17610000 0x1000>;
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clocks = <&cmu_apm CLK_GOUT_APM_MAILBOX_APM_AP_PCLK>;
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clock-names = "pclk";
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interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH 0>;
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#mbox-cells = <0>;
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};
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};

‎Documentation/devicetree/bindings/mailbox/microchip,sbi-ipc.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/mailbox/microchip,sbi-ipc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Microchip Inter-processor communication (IPC) mailbox controller
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maintainers:
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- Valentina Fernandez <valentina.fernandezalanis@microchip.com>
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description:
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The Microchip Inter-processor Communication (IPC) facilitates
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message passing between processors using an interrupt signaling
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mechanism.
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properties:
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compatible:
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oneOf:
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- description:
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Intended for use by software running in supervisor privileged
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mode (s-mode). This SBI interface is compatible with the Mi-V
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Inter-hart Communication (IHC) IP.
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const: microchip,sbi-ipc
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- description:
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Intended for use by the SBI implementation in machine mode
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(m-mode), this compatible string is for the MIV_IHC Soft-IP.
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const: microchip,miv-ihc-rtl-v2
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reg:
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maxItems: 1
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interrupts:
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minItems: 1
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maxItems: 5
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interrupt-names:
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minItems: 1
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maxItems: 5
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items:
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enum:
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- hart-0
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- hart-1
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- hart-2
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- hart-3
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- hart-4
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- hart-5
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"#mbox-cells":
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description: >
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For "microchip,sbi-ipc", the cell represents the global "logical"
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channel IDs. The meaning of channel IDs are platform firmware dependent.
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For "microchip,miv-ihc-rtl-v2", the cell represents the physical
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channel and does not vary based on the platform firmware.
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const: 1
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microchip,ihc-chan-disabled-mask:
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description: >
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Represents the enable/disable state of the bi-directional IHC
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channels within the MIV-IHC IP configuration.
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A bit set to '1' indicates that the corresponding channel is disabled,
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and any read or write operations to that channel will return zero.
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A bit set to '0' indicates that the corresponding channel is enabled
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and will be accessible through its dedicated address range registers.
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The actual enable/disable state of each channel is determined by the
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IP block’s configuration.
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$ref: /schemas/types.yaml#/definitions/uint16
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maximum: 0x7fff
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default: 0
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required:
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- compatible
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- interrupts
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- interrupt-names
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- "#mbox-cells"
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allOf:
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- if:
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properties:
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compatible:
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contains:
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const: microchip,sbi-ipc
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then:
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properties:
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reg:
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not: {}
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description:
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The 'microchip,sbi-ipc' operates in a programming model
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that does not require memory-mapped I/O (MMIO) registers
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since it uses SBI ecalls provided by the m-mode/firmware
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SBI implementation to access hardware registers.
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microchip,ihc-chan-disabled-mask: false
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else:
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required:
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- reg
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- microchip,ihc-chan-disabled-mask
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additionalProperties: false
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examples:
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- |
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mailbox {
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compatible = "microchip,sbi-ipc";
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interrupt-parent = <&plic>;
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interrupts = <180>, <179>, <178>;
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interrupt-names = "hart-1", "hart-2", "hart-3";
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#mbox-cells = <1>;
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};
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- |
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mailbox@50000000 {
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compatible = "microchip,miv-ihc-rtl-v2";
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microchip,ihc-chan-disabled-mask = /bits/ 16 <0>;
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reg = <0x50000000 0x1c000>;
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interrupt-parent = <&plic>;
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interrupts = <180>, <179>, <178>;
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interrupt-names = "hart-1", "hart-2", "hart-3";
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#mbox-cells = <1>;
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};

‎Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml

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- enum:
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- qcom,ipq5018-apcs-apps-global
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- qcom,ipq5332-apcs-apps-global
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- qcom,ipq5424-apcs-apps-global
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- qcom,ipq8074-apcs-apps-global
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- qcom,ipq9574-apcs-apps-global
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- const: qcom,ipq6018-apcs-apps-global

‎MAINTAINERS

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F: drivers/*/*s3c64xx*
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F: drivers/*/*s5pv210*
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F: drivers/clocksource/samsung_pwm_timer.c
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F: drivers/mailbox/exynos-mailbox.c
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F: drivers/memory/samsung/
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F: drivers/pwm/pwm-samsung.c
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F: drivers/soc/samsung/
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F: drivers/clk/samsung/clk-exynos850.c
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F: include/dt-bindings/clock/exynos850.h
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SAMSUNG EXYNOS MAILBOX DRIVER
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M: Tudor Ambarus <tudor.ambarus@linaro.org>
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L: linux-kernel@vger.kernel.org
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L: linux-samsung-soc@vger.kernel.org
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S: Supported
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F: Documentation/devicetree/bindings/mailbox/google,gs101-mbox.yaml
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F: drivers/mailbox/exynos-mailbox.c
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F: include/linux/mailbox/exynos-message.h
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SAMSUNG EXYNOS PSEUDO RANDOM NUMBER GENERATOR (RNG) DRIVER
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M: Krzysztof Kozlowski <krzk@kernel.org>
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L: linux-crypto@vger.kernel.org

‎arch/riscv/include/asm/vendorid_list.h

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#define ASM_VENDOR_LIST_H
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#define ANDES_VENDOR_ID 0x31e
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#define MICROCHIP_VENDOR_ID 0x029
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#define SIFIVE_VENDOR_ID 0x489
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#define THEAD_VENDOR_ID 0x5b7
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‎arch/riscv/kernel/smp.c

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unsigned long __cpuid_to_hartid_map[NR_CPUS] __ro_after_init = {
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[0 ... NR_CPUS-1] = INVALID_HARTID
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};
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EXPORT_SYMBOL_GPL(__cpuid_to_hartid_map);
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void __init smp_setup_processor_id(void)
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{

‎drivers/mailbox/Kconfig

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that provides different means of transports: supported extensions
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will be discovered and possibly managed at probe-time.
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config EXYNOS_MBOX
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tristate "Exynos Mailbox"
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depends on ARCH_EXYNOS || COMPILE_TEST
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help
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Say Y here if you want to build the Samsung Exynos Mailbox controller
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driver. The controller has 16 flag bits for hardware interrupt
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generation and a shared register for passing mailbox messages.
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When the controller is used by the ACPM interface the shared register
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is ignored and the mailbox controller acts as a doorbell that raises
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the interrupt to the ACPM firmware.
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config IMX_MBOX
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tristate "i.MX Mailbox"
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depends on ARCH_MXC || COMPILE_TEST
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If unsure, say N.
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config MCHP_SBI_IPC_MBOX
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tristate "Microchip Inter-processor Communication (IPC) SBI driver"
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depends on RISCV_SBI || COMPILE_TEST
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depends on ARCH_MICROCHIP
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help
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Mailbox implementation for Microchip devices with an
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Inter-process communication (IPC) controller.
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To compile this driver as a module, choose M here. the
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module will be called mailbox-mchp-ipc-sbi.
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If unsure, say N.
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config QCOM_APCS_IPC
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tristate "Qualcomm APCS IPC driver"
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depends on ARCH_QCOM || COMPILE_TEST

‎drivers/mailbox/Makefile

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obj-$(CONFIG_ARM_MHU_V3) += arm_mhuv3.o
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obj-$(CONFIG_EXYNOS_MBOX) += exynos-mailbox.o
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obj-$(CONFIG_IMX_MBOX) += imx-mailbox.o
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obj-$(CONFIG_ARMADA_37XX_RWTM_MBOX) += armada-37xx-rwtm-mailbox.o
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obj-$(CONFIG_POLARFIRE_SOC_MAILBOX) += mailbox-mpfs.o
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obj-$(CONFIG_MCHP_SBI_IPC_MBOX) += mailbox-mchp-ipc-sbi.o
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obj-$(CONFIG_QCOM_APCS_IPC) += qcom-apcs-ipc-mailbox.o
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obj-$(CONFIG_TEGRA_HSP_MBOX) += tegra-hsp.o

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