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Shin Sonkrzk
Shin Son
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krzk
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clk: samsung: exynosautov920: add cpucl1/2 clock support
Register compatible and cmu_info data to support clock CPUCL1/2 (CPU Cluster 1 and CPU Cluster 2), these provide clock for CPUCL1/2_SWTICH/CLUSTER. These clocks are required early during boot for the CPUs, so they are declared using CLK_OF_DECLARE instead of being registered through a platform driver. Signed-off-by: Shin Son <shin.son@samsung.com> Link: https://lore.kernel.org/r/20250428113517.426987-3-shin.son@samsung.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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‎drivers/clk/samsung/clk-exynosautov920.c

Lines changed: 206 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -19,6 +19,8 @@
1919
/* NOTE: Must be equal to the last clock ID increased by one */
2020
#define CLKS_NR_TOP (DOUT_CLKCMU_TAA_NOC + 1)
2121
#define CLKS_NR_CPUCL0 (CLK_DOUT_CLUSTER0_PERIPHCLK + 1)
22+
#define CLKS_NR_CPUCL1 (CLK_DOUT_CPUCL1_NOCP + 1)
23+
#define CLKS_NR_CPUCL2 (CLK_DOUT_CPUCL2_NOCP + 1)
2224
#define CLKS_NR_PERIC0 (CLK_DOUT_PERIC0_I3C + 1)
2325
#define CLKS_NR_PERIC1 (CLK_DOUT_PERIC1_I3C + 1)
2426
#define CLKS_NR_MISC (CLK_DOUT_MISC_OSC_DIV2 + 1)
@@ -1135,6 +1137,210 @@ static void __init exynosautov920_cmu_cpucl0_init(struct device_node *np)
11351137
CLK_OF_DECLARE(exynosautov920_cmu_cpucl0, "samsung,exynosautov920-cmu-cpucl0",
11361138
exynosautov920_cmu_cpucl0_init);
11371139

1140+
/* ---- CMU_CPUCL1 --------------------------------------------------------- */
1141+
1142+
/* Register Offset definitions for CMU_CPUCL1 (0x1ED00000) */
1143+
#define PLL_LOCKTIME_PLL_CPUCL1 0x0000
1144+
#define PLL_CON0_PLL_CPUCL1 0x0100
1145+
#define PLL_CON1_PLL_CPUCL1 0x0104
1146+
#define PLL_CON3_PLL_CPUCL1 0x010c
1147+
#define PLL_CON0_MUX_CLKCMU_CPUCL1_CLUSTER_USER 0x0600
1148+
#define PLL_CON0_MUX_CLKCMU_CPUCL1_SWITCH_USER 0x0610
1149+
1150+
#define CLK_CON_MUX_MUX_CLK_CPUCL1_CLUSTER 0x1000
1151+
#define CLK_CON_MUX_MUX_CLK_CPUCL1_CORE 0x1004
1152+
1153+
#define CLK_CON_DIV_DIV_CLK_CLUSTER1_ACLK 0x1800
1154+
#define CLK_CON_DIV_DIV_CLK_CLUSTER1_ATCLK 0x1804
1155+
#define CLK_CON_DIV_DIV_CLK_CLUSTER1_MPCLK 0x1808
1156+
#define CLK_CON_DIV_DIV_CLK_CLUSTER1_PCLK 0x180c
1157+
#define CLK_CON_DIV_DIV_CLK_CLUSTER1_PERIPHCLK 0x1810
1158+
#define CLK_CON_DIV_DIV_CLK_CPUCL1_NOCP 0x181c
1159+
1160+
static const unsigned long cpucl1_clk_regs[] __initconst = {
1161+
PLL_LOCKTIME_PLL_CPUCL1,
1162+
PLL_CON0_PLL_CPUCL1,
1163+
PLL_CON1_PLL_CPUCL1,
1164+
PLL_CON3_PLL_CPUCL1,
1165+
PLL_CON0_MUX_CLKCMU_CPUCL1_CLUSTER_USER,
1166+
PLL_CON0_MUX_CLKCMU_CPUCL1_SWITCH_USER,
1167+
CLK_CON_MUX_MUX_CLK_CPUCL1_CLUSTER,
1168+
CLK_CON_MUX_MUX_CLK_CPUCL1_CORE,
1169+
CLK_CON_DIV_DIV_CLK_CLUSTER1_ACLK,
1170+
CLK_CON_DIV_DIV_CLK_CLUSTER1_ATCLK,
1171+
CLK_CON_DIV_DIV_CLK_CLUSTER1_MPCLK,
1172+
CLK_CON_DIV_DIV_CLK_CLUSTER1_PCLK,
1173+
CLK_CON_DIV_DIV_CLK_CLUSTER1_PERIPHCLK,
1174+
CLK_CON_DIV_DIV_CLK_CPUCL1_NOCP,
1175+
};
1176+
1177+
/* List of parent clocks for Muxes in CMU_CPUCL1 */
1178+
PNAME(mout_pll_cpucl1_p) = { "oscclk", "fout_cpucl1_pll" };
1179+
PNAME(mout_cpucl1_cluster_user_p) = { "oscclk", "dout_clkcmu_cpucl1_cluster" };
1180+
PNAME(mout_cpucl1_switch_user_p) = { "oscclk", "dout_clkcmu_cpucl1_switch" };
1181+
PNAME(mout_cpucl1_cluster_p) = { "oscclk", "mout_cpucl1_cluster_user",
1182+
"mout_cpucl1_switch_user"};
1183+
PNAME(mout_cpucl1_core_p) = { "oscclk", "mout_pll_cpucl1",
1184+
"mout_cpucl1_switch_user"};
1185+
1186+
static const struct samsung_pll_clock cpucl1_pll_clks[] __initconst = {
1187+
/* CMU_CPUCL1_PURECLKCOMP */
1188+
PLL(pll_531x, CLK_FOUT_CPUCL1_PLL, "fout_cpucl1_pll", "oscclk",
1189+
PLL_LOCKTIME_PLL_CPUCL1, PLL_CON3_PLL_CPUCL1, cpu_pll_rates),
1190+
};
1191+
1192+
static const struct samsung_mux_clock cpucl1_mux_clks[] __initconst = {
1193+
MUX(CLK_MOUT_PLL_CPUCL1, "mout_pll_cpucl1", mout_pll_cpucl1_p,
1194+
PLL_CON0_PLL_CPUCL1, 4, 1),
1195+
MUX(CLK_MOUT_CPUCL1_CLUSTER_USER, "mout_cpucl1_cluster_user", mout_cpucl1_cluster_user_p,
1196+
PLL_CON0_MUX_CLKCMU_CPUCL1_CLUSTER_USER, 4, 1),
1197+
MUX(CLK_MOUT_CPUCL1_SWITCH_USER, "mout_cpucl1_switch_user", mout_cpucl1_switch_user_p,
1198+
PLL_CON0_MUX_CLKCMU_CPUCL1_SWITCH_USER, 4, 1),
1199+
MUX(CLK_MOUT_CPUCL1_CLUSTER, "mout_cpucl1_cluster", mout_cpucl1_cluster_p,
1200+
CLK_CON_MUX_MUX_CLK_CPUCL1_CLUSTER, 0, 2),
1201+
MUX(CLK_MOUT_CPUCL1_CORE, "mout_cpucl1_core", mout_cpucl1_core_p,
1202+
CLK_CON_MUX_MUX_CLK_CPUCL1_CORE, 0, 2),
1203+
};
1204+
1205+
static const struct samsung_div_clock cpucl1_div_clks[] __initconst = {
1206+
DIV(CLK_DOUT_CLUSTER1_ACLK, "dout_cluster1_aclk",
1207+
"mout_cpucl1_cluster", CLK_CON_DIV_DIV_CLK_CLUSTER1_ACLK, 0, 4),
1208+
DIV(CLK_DOUT_CLUSTER1_ATCLK, "dout_cluster1_atclk",
1209+
"mout_cpucl1_cluster", CLK_CON_DIV_DIV_CLK_CLUSTER1_ATCLK, 0, 4),
1210+
DIV(CLK_DOUT_CLUSTER1_MPCLK, "dout_cluster1_mpclk",
1211+
"mout_cpucl1_cluster", CLK_CON_DIV_DIV_CLK_CLUSTER1_MPCLK, 0, 4),
1212+
DIV(CLK_DOUT_CLUSTER1_PCLK, "dout_cluster1_pclk",
1213+
"mout_cpucl1_cluster", CLK_CON_DIV_DIV_CLK_CLUSTER1_PCLK, 0, 4),
1214+
DIV(CLK_DOUT_CLUSTER1_PERIPHCLK, "dout_cluster1_periphclk",
1215+
"mout_cpucl1_cluster", CLK_CON_DIV_DIV_CLK_CLUSTER1_PERIPHCLK, 0, 4),
1216+
DIV(CLK_DOUT_CPUCL1_NOCP, "dout_cpucl1_nocp",
1217+
"mout_cpucl1_cluster", CLK_CON_DIV_DIV_CLK_CPUCL1_NOCP, 0, 4),
1218+
};
1219+
1220+
static const struct samsung_cmu_info cpucl1_cmu_info __initconst = {
1221+
.pll_clks = cpucl1_pll_clks,
1222+
.nr_pll_clks = ARRAY_SIZE(cpucl1_pll_clks),
1223+
.mux_clks = cpucl1_mux_clks,
1224+
.nr_mux_clks = ARRAY_SIZE(cpucl1_mux_clks),
1225+
.div_clks = cpucl1_div_clks,
1226+
.nr_div_clks = ARRAY_SIZE(cpucl1_div_clks),
1227+
.nr_clk_ids = CLKS_NR_CPUCL1,
1228+
.clk_regs = cpucl1_clk_regs,
1229+
.nr_clk_regs = ARRAY_SIZE(cpucl1_clk_regs),
1230+
.clk_name = "cpucl1",
1231+
};
1232+
1233+
static void __init exynosautov920_cmu_cpucl1_init(struct device_node *np)
1234+
{
1235+
exynos_arm64_register_cmu(NULL, np, &cpucl1_cmu_info);
1236+
}
1237+
1238+
/* Register CMU_CPUCL1 early, as CPU clocks should be available ASAP */
1239+
CLK_OF_DECLARE(exynosautov920_cmu_cpucl1, "samsung,exynosautov920-cmu-cpucl1",
1240+
exynosautov920_cmu_cpucl1_init);
1241+
1242+
/* ---- CMU_CPUCL2 --------------------------------------------------------- */
1243+
1244+
/* Register Offset definitions for CMU_CPUCL2 (0x1EE00000) */
1245+
#define PLL_LOCKTIME_PLL_CPUCL2 0x0000
1246+
#define PLL_CON0_PLL_CPUCL2 0x0100
1247+
#define PLL_CON1_PLL_CPUCL2 0x0104
1248+
#define PLL_CON3_PLL_CPUCL2 0x010c
1249+
#define PLL_CON0_MUX_CLKCMU_CPUCL2_CLUSTER_USER 0x0600
1250+
#define PLL_CON0_MUX_CLKCMU_CPUCL2_SWITCH_USER 0x0610
1251+
1252+
#define CLK_CON_MUX_MUX_CLK_CPUCL2_CLUSTER 0x1000
1253+
#define CLK_CON_MUX_MUX_CLK_CPUCL2_CORE 0x1004
1254+
1255+
#define CLK_CON_DIV_DIV_CLK_CLUSTER2_ACLK 0x1800
1256+
#define CLK_CON_DIV_DIV_CLK_CLUSTER2_ATCLK 0x1804
1257+
#define CLK_CON_DIV_DIV_CLK_CLUSTER2_MPCLK 0x1808
1258+
#define CLK_CON_DIV_DIV_CLK_CLUSTER2_PCLK 0x180c
1259+
#define CLK_CON_DIV_DIV_CLK_CLUSTER2_PERIPHCLK 0x1810
1260+
#define CLK_CON_DIV_DIV_CLK_CPUCL2_NOCP 0x181c
1261+
1262+
static const unsigned long cpucl2_clk_regs[] __initconst = {
1263+
PLL_LOCKTIME_PLL_CPUCL2,
1264+
PLL_CON0_PLL_CPUCL2,
1265+
PLL_CON1_PLL_CPUCL2,
1266+
PLL_CON3_PLL_CPUCL2,
1267+
PLL_CON0_MUX_CLKCMU_CPUCL2_CLUSTER_USER,
1268+
PLL_CON0_MUX_CLKCMU_CPUCL2_SWITCH_USER,
1269+
CLK_CON_MUX_MUX_CLK_CPUCL2_CLUSTER,
1270+
CLK_CON_MUX_MUX_CLK_CPUCL2_CORE,
1271+
CLK_CON_DIV_DIV_CLK_CLUSTER2_ACLK,
1272+
CLK_CON_DIV_DIV_CLK_CLUSTER2_ATCLK,
1273+
CLK_CON_DIV_DIV_CLK_CLUSTER2_MPCLK,
1274+
CLK_CON_DIV_DIV_CLK_CLUSTER2_PCLK,
1275+
CLK_CON_DIV_DIV_CLK_CLUSTER2_PERIPHCLK,
1276+
CLK_CON_DIV_DIV_CLK_CPUCL2_NOCP,
1277+
};
1278+
1279+
/* List of parent clocks for Muxes in CMU_CPUCL2 */
1280+
PNAME(mout_pll_cpucl2_p) = { "oscclk", "fout_cpucl2_pll" };
1281+
PNAME(mout_cpucl2_cluster_user_p) = { "oscclk", "dout_clkcmu_cpucl2_cluster" };
1282+
PNAME(mout_cpucl2_switch_user_p) = { "oscclk", "dout_clkcmu_cpucl2_switch" };
1283+
PNAME(mout_cpucl2_cluster_p) = { "oscclk", "mout_cpucl2_cluster_user",
1284+
"mout_cpucl2_switch_user"};
1285+
PNAME(mout_cpucl2_core_p) = { "oscclk", "mout_pll_cpucl2",
1286+
"mout_cpucl2_switch_user"};
1287+
1288+
static const struct samsung_pll_clock cpucl2_pll_clks[] __initconst = {
1289+
/* CMU_CPUCL2_PURECLKCOMP */
1290+
PLL(pll_531x, CLK_FOUT_CPUCL2_PLL, "fout_cpucl2_pll", "oscclk",
1291+
PLL_LOCKTIME_PLL_CPUCL2, PLL_CON3_PLL_CPUCL2, cpu_pll_rates),
1292+
};
1293+
1294+
static const struct samsung_mux_clock cpucl2_mux_clks[] __initconst = {
1295+
MUX(CLK_MOUT_PLL_CPUCL2, "mout_pll_cpucl2", mout_pll_cpucl2_p,
1296+
PLL_CON0_PLL_CPUCL2, 4, 1),
1297+
MUX(CLK_MOUT_CPUCL2_CLUSTER_USER, "mout_cpucl2_cluster_user", mout_cpucl2_cluster_user_p,
1298+
PLL_CON0_MUX_CLKCMU_CPUCL2_CLUSTER_USER, 4, 1),
1299+
MUX(CLK_MOUT_CPUCL2_SWITCH_USER, "mout_cpucl2_switch_user", mout_cpucl2_switch_user_p,
1300+
PLL_CON0_MUX_CLKCMU_CPUCL2_SWITCH_USER, 4, 1),
1301+
MUX(CLK_MOUT_CPUCL2_CLUSTER, "mout_cpucl2_cluster", mout_cpucl2_cluster_p,
1302+
CLK_CON_MUX_MUX_CLK_CPUCL2_CLUSTER, 0, 2),
1303+
MUX(CLK_MOUT_CPUCL2_CORE, "mout_cpucl2_core", mout_cpucl2_core_p,
1304+
CLK_CON_MUX_MUX_CLK_CPUCL2_CORE, 0, 2),
1305+
};
1306+
1307+
static const struct samsung_div_clock cpucl2_div_clks[] __initconst = {
1308+
DIV(CLK_DOUT_CLUSTER2_ACLK, "dout_cluster2_aclk",
1309+
"mout_cpucl2_cluster", CLK_CON_DIV_DIV_CLK_CLUSTER2_ACLK, 0, 4),
1310+
DIV(CLK_DOUT_CLUSTER2_ATCLK, "dout_cluster2_atclk",
1311+
"mout_cpucl2_cluster", CLK_CON_DIV_DIV_CLK_CLUSTER2_ATCLK, 0, 4),
1312+
DIV(CLK_DOUT_CLUSTER2_MPCLK, "dout_cluster2_mpclk",
1313+
"mout_cpucl2_cluster", CLK_CON_DIV_DIV_CLK_CLUSTER2_MPCLK, 0, 4),
1314+
DIV(CLK_DOUT_CLUSTER2_PCLK, "dout_cluster2_pclk",
1315+
"mout_cpucl2_cluster", CLK_CON_DIV_DIV_CLK_CLUSTER2_PCLK, 0, 4),
1316+
DIV(CLK_DOUT_CLUSTER2_PERIPHCLK, "dout_cluster2_periphclk",
1317+
"mout_cpucl2_cluster", CLK_CON_DIV_DIV_CLK_CLUSTER2_PERIPHCLK, 0, 4),
1318+
DIV(CLK_DOUT_CPUCL2_NOCP, "dout_cpucl2_nocp",
1319+
"mout_cpucl2_cluster", CLK_CON_DIV_DIV_CLK_CPUCL2_NOCP, 0, 4),
1320+
};
1321+
1322+
static const struct samsung_cmu_info cpucl2_cmu_info __initconst = {
1323+
.pll_clks = cpucl2_pll_clks,
1324+
.nr_pll_clks = ARRAY_SIZE(cpucl2_pll_clks),
1325+
.mux_clks = cpucl2_mux_clks,
1326+
.nr_mux_clks = ARRAY_SIZE(cpucl2_mux_clks),
1327+
.div_clks = cpucl2_div_clks,
1328+
.nr_div_clks = ARRAY_SIZE(cpucl2_div_clks),
1329+
.nr_clk_ids = CLKS_NR_CPUCL2,
1330+
.clk_regs = cpucl2_clk_regs,
1331+
.nr_clk_regs = ARRAY_SIZE(cpucl2_clk_regs),
1332+
.clk_name = "cpucl2",
1333+
};
1334+
1335+
static void __init exynosautov920_cmu_cpucl2_init(struct device_node *np)
1336+
{
1337+
exynos_arm64_register_cmu(NULL, np, &cpucl2_cmu_info);
1338+
}
1339+
1340+
/* Register CMU_CPUCL2 early, as CPU clocks should be available ASAP */
1341+
CLK_OF_DECLARE(exynosautov920_cmu_cpucl2, "samsung,exynosautov920-cmu-cpucl2",
1342+
exynosautov920_cmu_cpucl2_init);
1343+
11381344
/* ---- CMU_PERIC0 --------------------------------------------------------- */
11391345

11401346
/* Register Offset definitions for CMU_PERIC0 (0x10800000) */

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