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clk: qcom: gcc-sc8280xp: don't use parking clk_ops for QUPs
A recent change started parking the RCG at an always on parent during registration, something which specifically breaks handover from an early serial console. Quoting Stephen Boyd who fixed this issue for SM8550 [1]: The QUPs aren't shared in a way that requires parking the RCG at an always on parent in case some other entity turns on the clk. The hardware is capable of setting a new frequency itself with the DFS mode, so parking is unnecessary. Furthermore, there aren't any GDSCs for these devices, so there isn't a possibility of the GDSC turning on the clks for housekeeping purposes. This wasn't a problem to mark these clks shared until we started parking shared RCGs at clk registration time in commit 01a0a6c ("clk: qcom: Park shared RCGs upon registration"). Parking at init is actually harmful to the UART when earlycon is used. If the device is pumping out data while the frequency changes you'll see garbage on the serial console until the driver can probe and actually set a proper frequency. Fixes: 01a0a6c ("clk: qcom: Park shared RCGs upon registration") Fixes: d65d005 ("clk: qcom: add sc8280xp GCC driver") Link: https://lore.kernel.org/all/20240819233628.2074654-2-swboyd@chromium.org/ [1] Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Link: https://lore.kernel.org/r/20240902070830.8535-1-johan+linaro@kernel.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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‎drivers/clk/qcom/gcc-sc8280xp.c

Lines changed: 24 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -1500,7 +1500,7 @@ static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = {
15001500
.parent_data = gcc_parent_data_0,
15011501
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
15021502
.flags = CLK_SET_RATE_PARENT,
1503-
.ops = &clk_rcg2_shared_ops,
1503+
.ops = &clk_rcg2_ops,
15041504
};
15051505

15061506
static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = {
@@ -1517,7 +1517,7 @@ static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = {
15171517
.parent_data = gcc_parent_data_0,
15181518
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
15191519
.flags = CLK_SET_RATE_PARENT,
1520-
.ops = &clk_rcg2_shared_ops,
1520+
.ops = &clk_rcg2_ops,
15211521
};
15221522

15231523
static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = {
@@ -1534,7 +1534,7 @@ static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = {
15341534
.parent_data = gcc_parent_data_0,
15351535
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
15361536
.flags = CLK_SET_RATE_PARENT,
1537-
.ops = &clk_rcg2_shared_ops,
1537+
.ops = &clk_rcg2_ops,
15381538
};
15391539

15401540
static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = {
@@ -1551,7 +1551,7 @@ static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = {
15511551
.parent_data = gcc_parent_data_0,
15521552
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
15531553
.flags = CLK_SET_RATE_PARENT,
1554-
.ops = &clk_rcg2_shared_ops,
1554+
.ops = &clk_rcg2_ops,
15551555
};
15561556

15571557
static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = {
@@ -1568,7 +1568,7 @@ static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = {
15681568
.parent_data = gcc_parent_data_0,
15691569
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
15701570
.flags = CLK_SET_RATE_PARENT,
1571-
.ops = &clk_rcg2_shared_ops,
1571+
.ops = &clk_rcg2_ops,
15721572
};
15731573

15741574
static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = {
@@ -1585,7 +1585,7 @@ static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = {
15851585
.parent_data = gcc_parent_data_0,
15861586
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
15871587
.flags = CLK_SET_RATE_PARENT,
1588-
.ops = &clk_rcg2_shared_ops,
1588+
.ops = &clk_rcg2_ops,
15891589
};
15901590

15911591
static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = {
@@ -1617,7 +1617,7 @@ static struct clk_init_data gcc_qupv3_wrap0_s6_clk_src_init = {
16171617
.parent_data = gcc_parent_data_0,
16181618
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
16191619
.flags = CLK_SET_RATE_PARENT,
1620-
.ops = &clk_rcg2_shared_ops,
1620+
.ops = &clk_rcg2_ops,
16211621
};
16221622

16231623
static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = {
@@ -1634,7 +1634,7 @@ static struct clk_init_data gcc_qupv3_wrap0_s7_clk_src_init = {
16341634
.parent_data = gcc_parent_data_0,
16351635
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
16361636
.flags = CLK_SET_RATE_PARENT,
1637-
.ops = &clk_rcg2_shared_ops,
1637+
.ops = &clk_rcg2_ops,
16381638
};
16391639

16401640
static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = {
@@ -1651,7 +1651,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = {
16511651
.parent_data = gcc_parent_data_0,
16521652
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
16531653
.flags = CLK_SET_RATE_PARENT,
1654-
.ops = &clk_rcg2_shared_ops,
1654+
.ops = &clk_rcg2_ops,
16551655
};
16561656

16571657
static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {
@@ -1668,7 +1668,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = {
16681668
.parent_data = gcc_parent_data_0,
16691669
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
16701670
.flags = CLK_SET_RATE_PARENT,
1671-
.ops = &clk_rcg2_shared_ops,
1671+
.ops = &clk_rcg2_ops,
16721672
};
16731673

16741674
static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = {
@@ -1685,7 +1685,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = {
16851685
.parent_data = gcc_parent_data_0,
16861686
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
16871687
.flags = CLK_SET_RATE_PARENT,
1688-
.ops = &clk_rcg2_shared_ops,
1688+
.ops = &clk_rcg2_ops,
16891689
};
16901690

16911691
static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = {
@@ -1702,7 +1702,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = {
17021702
.parent_data = gcc_parent_data_0,
17031703
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
17041704
.flags = CLK_SET_RATE_PARENT,
1705-
.ops = &clk_rcg2_shared_ops,
1705+
.ops = &clk_rcg2_ops,
17061706
};
17071707

17081708
static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = {
@@ -1719,7 +1719,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = {
17191719
.parent_data = gcc_parent_data_0,
17201720
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
17211721
.flags = CLK_SET_RATE_PARENT,
1722-
.ops = &clk_rcg2_shared_ops,
1722+
.ops = &clk_rcg2_ops,
17231723
};
17241724

17251725
static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = {
@@ -1736,7 +1736,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = {
17361736
.parent_data = gcc_parent_data_0,
17371737
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
17381738
.flags = CLK_SET_RATE_PARENT,
1739-
.ops = &clk_rcg2_shared_ops,
1739+
.ops = &clk_rcg2_ops,
17401740
};
17411741

17421742
static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = {
@@ -1753,7 +1753,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s6_clk_src_init = {
17531753
.parent_data = gcc_parent_data_0,
17541754
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
17551755
.flags = CLK_SET_RATE_PARENT,
1756-
.ops = &clk_rcg2_shared_ops,
1756+
.ops = &clk_rcg2_ops,
17571757
};
17581758

17591759
static struct clk_rcg2 gcc_qupv3_wrap1_s6_clk_src = {
@@ -1770,7 +1770,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s7_clk_src_init = {
17701770
.parent_data = gcc_parent_data_0,
17711771
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
17721772
.flags = CLK_SET_RATE_PARENT,
1773-
.ops = &clk_rcg2_shared_ops,
1773+
.ops = &clk_rcg2_ops,
17741774
};
17751775

17761776
static struct clk_rcg2 gcc_qupv3_wrap1_s7_clk_src = {
@@ -1787,7 +1787,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s0_clk_src_init = {
17871787
.parent_data = gcc_parent_data_0,
17881788
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
17891789
.flags = CLK_SET_RATE_PARENT,
1790-
.ops = &clk_rcg2_shared_ops,
1790+
.ops = &clk_rcg2_ops,
17911791
};
17921792

17931793
static struct clk_rcg2 gcc_qupv3_wrap2_s0_clk_src = {
@@ -1804,7 +1804,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s1_clk_src_init = {
18041804
.parent_data = gcc_parent_data_0,
18051805
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
18061806
.flags = CLK_SET_RATE_PARENT,
1807-
.ops = &clk_rcg2_shared_ops,
1807+
.ops = &clk_rcg2_ops,
18081808
};
18091809

18101810
static struct clk_rcg2 gcc_qupv3_wrap2_s1_clk_src = {
@@ -1821,7 +1821,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s2_clk_src_init = {
18211821
.parent_data = gcc_parent_data_0,
18221822
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
18231823
.flags = CLK_SET_RATE_PARENT,
1824-
.ops = &clk_rcg2_shared_ops,
1824+
.ops = &clk_rcg2_ops,
18251825
};
18261826

18271827
static struct clk_rcg2 gcc_qupv3_wrap2_s2_clk_src = {
@@ -1838,7 +1838,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s3_clk_src_init = {
18381838
.parent_data = gcc_parent_data_0,
18391839
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
18401840
.flags = CLK_SET_RATE_PARENT,
1841-
.ops = &clk_rcg2_shared_ops,
1841+
.ops = &clk_rcg2_ops,
18421842
};
18431843

18441844
static struct clk_rcg2 gcc_qupv3_wrap2_s3_clk_src = {
@@ -1855,7 +1855,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s4_clk_src_init = {
18551855
.parent_data = gcc_parent_data_0,
18561856
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
18571857
.flags = CLK_SET_RATE_PARENT,
1858-
.ops = &clk_rcg2_shared_ops,
1858+
.ops = &clk_rcg2_ops,
18591859
};
18601860

18611861
static struct clk_rcg2 gcc_qupv3_wrap2_s4_clk_src = {
@@ -1872,7 +1872,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s5_clk_src_init = {
18721872
.parent_data = gcc_parent_data_0,
18731873
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
18741874
.flags = CLK_SET_RATE_PARENT,
1875-
.ops = &clk_rcg2_shared_ops,
1875+
.ops = &clk_rcg2_ops,
18761876
};
18771877

18781878
static struct clk_rcg2 gcc_qupv3_wrap2_s5_clk_src = {
@@ -1889,7 +1889,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s6_clk_src_init = {
18891889
.parent_data = gcc_parent_data_0,
18901890
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
18911891
.flags = CLK_SET_RATE_PARENT,
1892-
.ops = &clk_rcg2_shared_ops,
1892+
.ops = &clk_rcg2_ops,
18931893
};
18941894

18951895
static struct clk_rcg2 gcc_qupv3_wrap2_s6_clk_src = {
@@ -1906,7 +1906,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s7_clk_src_init = {
19061906
.parent_data = gcc_parent_data_0,
19071907
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
19081908
.flags = CLK_SET_RATE_PARENT,
1909-
.ops = &clk_rcg2_shared_ops,
1909+
.ops = &clk_rcg2_ops,
19101910
};
19111911

19121912
static struct clk_rcg2 gcc_qupv3_wrap2_s7_clk_src = {

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