Skip to content

Commit 6e1c795

Browse files
prabhakarladgeertu
authored andcommitted
clk: renesas: rzv2h: Add macro for defining static dividers
Unlike dynamic dividers, static dividers do not have a monitor bit. Introduce the `DEF_CSDIV()` macro for defining static dividers, ensuring consistency with existing dynamic divider macros. Additionally, introduce the `CSDIV_NO_MON` macro to indicate the absence of a monitor bit, allowing the monitoring step to be skipped when `mon` is set to `CSDIV_NO_MON`. Note, `rzv2h_cpg_ddiv_clk_register()` will be re-used instead of generic `clk_hw_register_divider_table()` for registering satic dividers as some of the static dividers require RMW operations. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250407165202.197570-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
1 parent c1d6f68 commit 6e1c795

File tree

2 files changed

+13
-0
lines changed

2 files changed

+13
-0
lines changed

drivers/clk/renesas/rzv2h-cpg.c

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -298,6 +298,9 @@ static inline int rzv2h_cpg_wait_ddiv_clk_update_done(void __iomem *base, u8 mon
298298
u32 bitmask = BIT(mon);
299299
u32 val;
300300

301+
if (mon == CSDIV_NO_MON)
302+
return 0;
303+
301304
return readl_poll_timeout_atomic(base + CPG_CLKSTATUS0, val, !(val & bitmask), 10, 200);
302305
}
303306

drivers/clk/renesas/rzv2h-cpg.h

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -45,6 +45,14 @@ struct ddiv {
4545
unsigned int monbit:5;
4646
};
4747

48+
/*
49+
* On RZ/V2H(P), the dynamic divider clock supports up to 19 monitor bits,
50+
* while on RZ/G3E, it supports up to 16 monitor bits. Use the maximum value
51+
* `0x1f` to indicate that monitor bits are not supported for static divider
52+
* clocks.
53+
*/
54+
#define CSDIV_NO_MON (0x1f)
55+
4856
#define DDIV_PACK(_offset, _shift, _width, _monbit) \
4957
((struct ddiv){ \
5058
.offset = _offset, \
@@ -150,6 +158,8 @@ enum clk_types {
150158
.parent = _parent, \
151159
.dtable = _dtable, \
152160
.flag = CLK_DIVIDER_HIWORD_MASK)
161+
#define DEF_CSDIV(_name, _id, _parent, _ddiv_packed, _dtable) \
162+
DEF_DDIV(_name, _id, _parent, _ddiv_packed, _dtable)
153163
#define DEF_SMUX(_name, _id, _smux_packed, _parent_names) \
154164
DEF_TYPE(_name, _id, CLK_TYPE_SMUX, \
155165
.cfg.smux = _smux_packed, \

0 commit comments

Comments
 (0)