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openrisc: Add cacheinfo support
Add cacheinfo support for OpenRISC. Currently, a few CPU cache attributes pertaining to OpenRISC processors are exposed along with other unrelated CPU attributes in the procfs file system (/proc/cpuinfo). However, a few cache attributes remain unexposed. Provide a mechanism that the generic cacheinfo infrastructure can employ to expose these attributes via the sysfs file system. These attributes can then be exposed in /sys/devices/system/cpu/cpuX/cache/indexN. Move the implementation to pull cache attributes from the processor's registers from arch/openrisc/kernel/setup.c with a few modifications. This implementation is based on similar work done for MIPS and LoongArch. Link: https://raw.githubusercontent.com/openrisc/doc/master/openrisc-arch-1.4-rev0.pdf Signed-off-by: Sahil Siddiq <sahilcdq0@gmail.com> Signed-off-by: Stafford Horne <shorne@gmail.com>
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+108
-42
lines changed

arch/openrisc/kernel/Makefile

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -7,7 +7,7 @@ extra-y := vmlinux.lds
77

88
obj-y := head.o setup.o or32_ksyms.o process.o dma.o \
99
traps.o time.o irq.o entry.o ptrace.o signal.o \
10-
sys_call_table.o unwinder.o
10+
sys_call_table.o unwinder.o cacheinfo.o
1111

1212
obj-$(CONFIG_SMP) += smp.o sync-timer.o
1313
obj-$(CONFIG_STACKTRACE) += stacktrace.o

arch/openrisc/kernel/cacheinfo.c

Lines changed: 104 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,104 @@
1+
// SPDX-License-Identifier: GPL-2.0-or-later
2+
/*
3+
* OpenRISC cacheinfo support
4+
*
5+
* Based on work done for MIPS and LoongArch. All original copyrights
6+
* apply as per the original source declaration.
7+
*
8+
* OpenRISC implementation:
9+
* Copyright (C) 2025 Sahil Siddiq <sahilcdq@proton.me>
10+
*/
11+
12+
#include <linux/cacheinfo.h>
13+
#include <asm/cpuinfo.h>
14+
#include <asm/spr.h>
15+
#include <asm/spr_defs.h>
16+
17+
static inline void ci_leaf_init(struct cacheinfo *this_leaf, enum cache_type type,
18+
unsigned int level, struct cache_desc *cache, int cpu)
19+
{
20+
this_leaf->type = type;
21+
this_leaf->level = level;
22+
this_leaf->coherency_line_size = cache->block_size;
23+
this_leaf->number_of_sets = cache->sets;
24+
this_leaf->ways_of_associativity = cache->ways;
25+
this_leaf->size = cache->size;
26+
cpumask_set_cpu(cpu, &this_leaf->shared_cpu_map);
27+
}
28+
29+
int init_cache_level(unsigned int cpu)
30+
{
31+
struct cpuinfo_or1k *cpuinfo = &cpuinfo_or1k[smp_processor_id()];
32+
struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu);
33+
int leaves = 0, levels = 0;
34+
unsigned long upr = mfspr(SPR_UPR);
35+
unsigned long iccfgr, dccfgr;
36+
37+
if (!(upr & SPR_UPR_UP)) {
38+
printk(KERN_INFO
39+
"-- no UPR register... unable to detect configuration\n");
40+
return -ENOENT;
41+
}
42+
43+
if (cpu_cache_is_present(SPR_UPR_DCP)) {
44+
dccfgr = mfspr(SPR_DCCFGR);
45+
cpuinfo->dcache.ways = 1 << (dccfgr & SPR_DCCFGR_NCW);
46+
cpuinfo->dcache.sets = 1 << ((dccfgr & SPR_DCCFGR_NCS) >> 3);
47+
cpuinfo->dcache.block_size = 16 << ((dccfgr & SPR_DCCFGR_CBS) >> 7);
48+
cpuinfo->dcache.size =
49+
cpuinfo->dcache.sets * cpuinfo->dcache.ways * cpuinfo->dcache.block_size;
50+
leaves += 1;
51+
printk(KERN_INFO
52+
"-- dcache: %d bytes total, %d bytes/line, %d set(s), %d way(s)\n",
53+
cpuinfo->dcache.size, cpuinfo->dcache.block_size,
54+
cpuinfo->dcache.sets, cpuinfo->dcache.ways);
55+
} else
56+
printk(KERN_INFO "-- dcache disabled\n");
57+
58+
if (cpu_cache_is_present(SPR_UPR_ICP)) {
59+
iccfgr = mfspr(SPR_ICCFGR);
60+
cpuinfo->icache.ways = 1 << (iccfgr & SPR_ICCFGR_NCW);
61+
cpuinfo->icache.sets = 1 << ((iccfgr & SPR_ICCFGR_NCS) >> 3);
62+
cpuinfo->icache.block_size = 16 << ((iccfgr & SPR_ICCFGR_CBS) >> 7);
63+
cpuinfo->icache.size =
64+
cpuinfo->icache.sets * cpuinfo->icache.ways * cpuinfo->icache.block_size;
65+
leaves += 1;
66+
printk(KERN_INFO
67+
"-- icache: %d bytes total, %d bytes/line, %d set(s), %d way(s)\n",
68+
cpuinfo->icache.size, cpuinfo->icache.block_size,
69+
cpuinfo->icache.sets, cpuinfo->icache.ways);
70+
} else
71+
printk(KERN_INFO "-- icache disabled\n");
72+
73+
if (!leaves)
74+
return -ENOENT;
75+
76+
levels = 1;
77+
78+
this_cpu_ci->num_leaves = leaves;
79+
this_cpu_ci->num_levels = levels;
80+
81+
return 0;
82+
}
83+
84+
int populate_cache_leaves(unsigned int cpu)
85+
{
86+
struct cpuinfo_or1k *cpuinfo = &cpuinfo_or1k[smp_processor_id()];
87+
struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu);
88+
struct cacheinfo *this_leaf = this_cpu_ci->info_list;
89+
int level = 1;
90+
91+
if (cpu_cache_is_present(SPR_UPR_DCP)) {
92+
ci_leaf_init(this_leaf, CACHE_TYPE_DATA, level, &cpuinfo->dcache, cpu);
93+
this_leaf->attributes = ((mfspr(SPR_DCCFGR) & SPR_DCCFGR_CWS) >> 8) ?
94+
CACHE_WRITE_BACK : CACHE_WRITE_THROUGH;
95+
this_leaf++;
96+
}
97+
98+
if (cpu_cache_is_present(SPR_UPR_ICP))
99+
ci_leaf_init(this_leaf, CACHE_TYPE_INST, level, &cpuinfo->icache, cpu);
100+
101+
this_cpu_ci->cpu_map_populated = true;
102+
103+
return 0;
104+
}

arch/openrisc/kernel/setup.c

Lines changed: 3 additions & 41 deletions
Original file line numberDiff line numberDiff line change
@@ -113,21 +113,6 @@ static void print_cpuinfo(void)
113113
return;
114114
}
115115

116-
if (upr & SPR_UPR_DCP)
117-
printk(KERN_INFO
118-
"-- dcache: %4d bytes total, %2d bytes/line, %d set(s), %d way(s)\n",
119-
cpuinfo->dcache.size, cpuinfo->dcache.block_size,
120-
cpuinfo->dcache.sets, cpuinfo->dcache.ways);
121-
else
122-
printk(KERN_INFO "-- dcache disabled\n");
123-
if (upr & SPR_UPR_ICP)
124-
printk(KERN_INFO
125-
"-- icache: %4d bytes total, %2d bytes/line, %d set(s), %d way(s)\n",
126-
cpuinfo->icache.size, cpuinfo->icache.block_size,
127-
cpuinfo->icache.sets, cpuinfo->icache.ways);
128-
else
129-
printk(KERN_INFO "-- icache disabled\n");
130-
131116
if (upr & SPR_UPR_DMP)
132117
printk(KERN_INFO "-- dmmu: %4d entries, %lu way(s)\n",
133118
1 << ((mfspr(SPR_DMMUCFGR) & SPR_DMMUCFGR_NTS) >> 2),
@@ -155,28 +140,13 @@ static void print_cpuinfo(void)
155140
void __init setup_cpuinfo(void)
156141
{
157142
struct device_node *cpu;
158-
unsigned long iccfgr, dccfgr;
159143
int cpu_id = smp_processor_id();
160144
struct cpuinfo_or1k *cpuinfo = &cpuinfo_or1k[cpu_id];
161145

162146
cpu = of_get_cpu_node(cpu_id, NULL);
163147
if (!cpu)
164148
panic("Couldn't find CPU%d in device tree...\n", cpu_id);
165149

166-
iccfgr = mfspr(SPR_ICCFGR);
167-
cpuinfo->icache.ways = 1 << (iccfgr & SPR_ICCFGR_NCW);
168-
cpuinfo->icache.sets = 1 << ((iccfgr & SPR_ICCFGR_NCS) >> 3);
169-
cpuinfo->icache.block_size = 16 << ((iccfgr & SPR_ICCFGR_CBS) >> 7);
170-
cpuinfo->icache.size =
171-
cpuinfo->icache.sets * cpuinfo->icache.ways * cpuinfo->icache.block_size;
172-
173-
dccfgr = mfspr(SPR_DCCFGR);
174-
cpuinfo->dcache.ways = 1 << (dccfgr & SPR_DCCFGR_NCW);
175-
cpuinfo->dcache.sets = 1 << ((dccfgr & SPR_DCCFGR_NCS) >> 3);
176-
cpuinfo->dcache.block_size = 16 << ((dccfgr & SPR_DCCFGR_CBS) >> 7);
177-
cpuinfo->dcache.size =
178-
cpuinfo->dcache.sets * cpuinfo->dcache.ways * cpuinfo->dcache.block_size;
179-
180150
if (of_property_read_u32(cpu, "clock-frequency",
181151
&cpuinfo->clock_frequency)) {
182152
printk(KERN_WARNING
@@ -293,14 +263,14 @@ static int show_cpuinfo(struct seq_file *m, void *v)
293263
unsigned int vr, cpucfgr;
294264
unsigned int avr;
295265
unsigned int version;
266+
#ifdef CONFIG_SMP
296267
struct cpuinfo_or1k *cpuinfo = v;
268+
seq_printf(m, "processor\t\t: %d\n", cpuinfo->coreid);
269+
#endif
297270

298271
vr = mfspr(SPR_VR);
299272
cpucfgr = mfspr(SPR_CPUCFGR);
300273

301-
#ifdef CONFIG_SMP
302-
seq_printf(m, "processor\t\t: %d\n", cpuinfo->coreid);
303-
#endif
304274
if (vr & SPR_VR_UVRP) {
305275
vr = mfspr(SPR_VR2);
306276
version = vr & SPR_VR2_VER;
@@ -319,14 +289,6 @@ static int show_cpuinfo(struct seq_file *m, void *v)
319289
seq_printf(m, "revision\t\t: %d\n", vr & SPR_VR_REV);
320290
}
321291
seq_printf(m, "frequency\t\t: %ld\n", loops_per_jiffy * HZ);
322-
seq_printf(m, "dcache size\t\t: %d bytes\n", cpuinfo->dcache.size);
323-
seq_printf(m, "dcache block size\t: %d bytes\n",
324-
cpuinfo->dcache.block_size);
325-
seq_printf(m, "dcache ways\t\t: %d\n", cpuinfo->dcache.ways);
326-
seq_printf(m, "icache size\t\t: %d bytes\n", cpuinfo->icache.size);
327-
seq_printf(m, "icache block size\t: %d bytes\n",
328-
cpuinfo->icache.block_size);
329-
seq_printf(m, "icache ways\t\t: %d\n", cpuinfo->icache.ways);
330292
seq_printf(m, "immu\t\t\t: %d entries, %lu ways\n",
331293
1 << ((mfspr(SPR_DMMUCFGR) & SPR_DMMUCFGR_NTS) >> 2),
332294
1 + (mfspr(SPR_DMMUCFGR) & SPR_DMMUCFGR_NTW));

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