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Merge tag 'kvm-riscv-6.13-2' of https://github.com/kvm-riscv/linux into HEAD
KVM/riscv changes for 6.13 part #2 - Svade and Svadu extension support for Host and Guest/VM
2 parents c166852 + c74bfe4 commit 4d911c7

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Documentation/devicetree/bindings/riscv/extensions.yaml

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Original file line numberDiff line numberDiff line change
@@ -171,6 +171,34 @@ properties:
171171
ratified at commit 3f9ed34 ("Add ability to manually trigger
172172
workflow. (#2)") of riscv-time-compare.
173173
174+
- const: svade
175+
description: |
176+
The standard Svade supervisor-level extension for SW-managed PTE A/D
177+
bit updates as ratified in the 20240213 version of the privileged
178+
ISA specification.
179+
180+
Both Svade and Svadu extensions control the hardware behavior when
181+
the PTE A/D bits need to be set. The default behavior for the four
182+
possible combinations of these extensions in the device tree are:
183+
1) Neither Svade nor Svadu present in DT => It is technically
184+
unknown whether the platform uses Svade or Svadu. Supervisor
185+
software should be prepared to handle either hardware updating
186+
of the PTE A/D bits or page faults when they need updated.
187+
2) Only Svade present in DT => Supervisor must assume Svade to be
188+
always enabled.
189+
3) Only Svadu present in DT => Supervisor must assume Svadu to be
190+
always enabled.
191+
4) Both Svade and Svadu present in DT => Supervisor must assume
192+
Svadu turned-off at boot time. To use Svadu, supervisor must
193+
explicitly enable it using the SBI FWFT extension.
194+
195+
- const: svadu
196+
description: |
197+
The standard Svadu supervisor-level extension for hardware updating
198+
of PTE A/D bits as ratified in the 20240528 version of the
199+
privileged ISA specification. Please refer to Svade dt-binding
200+
description for more details.
201+
174202
- const: svinval
175203
description:
176204
The standard Svinval supervisor-level extension for fine-grained

arch/riscv/Kconfig

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Original file line numberDiff line numberDiff line change
@@ -32,6 +32,7 @@ config RISCV
3232
select ARCH_HAS_FORTIFY_SOURCE
3333
select ARCH_HAS_GCOV_PROFILE_ALL
3434
select ARCH_HAS_GIGANTIC_PAGE
35+
select ARCH_HAS_HW_PTE_YOUNG
3536
select ARCH_HAS_KCOV
3637
select ARCH_HAS_KERNEL_FPU_SUPPORT if 64BIT && FPU
3738
select ARCH_HAS_MEMBARRIER_CALLBACKS

arch/riscv/include/asm/csr.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -199,6 +199,7 @@
199199
/* xENVCFG flags */
200200
#define ENVCFG_STCE (_AC(1, ULL) << 63)
201201
#define ENVCFG_PBMTE (_AC(1, ULL) << 62)
202+
#define ENVCFG_ADUE (_AC(1, ULL) << 61)
202203
#define ENVCFG_PMM (_AC(0x3, ULL) << 32)
203204
#define ENVCFG_PMM_PMLEN_0 (_AC(0x0, ULL) << 32)
204205
#define ENVCFG_PMM_PMLEN_7 (_AC(0x2, ULL) << 32)

arch/riscv/include/asm/hwcap.h

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -98,6 +98,8 @@
9898
#define RISCV_ISA_EXT_SSNPM 89
9999
#define RISCV_ISA_EXT_ZABHA 90
100100
#define RISCV_ISA_EXT_ZICCRSE 91
101+
#define RISCV_ISA_EXT_SVADE 92
102+
#define RISCV_ISA_EXT_SVADU 93
101103

102104
#define RISCV_ISA_EXT_XLINUXENVCFG 127
103105

arch/riscv/include/asm/pgtable.h

Lines changed: 12 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -113,6 +113,7 @@
113113
#include <asm/tlbflush.h>
114114
#include <linux/mm_types.h>
115115
#include <asm/compat.h>
116+
#include <asm/cpufeature.h>
116117

117118
#define __page_val_to_pfn(_val) (((_val) & _PAGE_PFN_MASK) >> _PAGE_PFN_SHIFT)
118119

@@ -284,7 +285,6 @@ static inline pte_t pud_pte(pud_t pud)
284285
}
285286

286287
#ifdef CONFIG_RISCV_ISA_SVNAPOT
287-
#include <asm/cpufeature.h>
288288

289289
static __always_inline bool has_svnapot(void)
290290
{
@@ -655,6 +655,17 @@ static inline pgprot_t pgprot_writecombine(pgprot_t _prot)
655655
return __pgprot(prot);
656656
}
657657

658+
/*
659+
* Both Svade and Svadu control the hardware behavior when the PTE A/D bits need to be set. By
660+
* default the M-mode firmware enables the hardware updating scheme when only Svadu is present in
661+
* DT.
662+
*/
663+
#define arch_has_hw_pte_young arch_has_hw_pte_young
664+
static inline bool arch_has_hw_pte_young(void)
665+
{
666+
return riscv_has_extension_unlikely(RISCV_ISA_EXT_SVADU);
667+
}
668+
658669
/*
659670
* THP functions
660671
*/

arch/riscv/include/uapi/asm/kvm.h

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -177,6 +177,8 @@ enum KVM_RISCV_ISA_EXT_ID {
177177
KVM_RISCV_ISA_EXT_ZAWRS,
178178
KVM_RISCV_ISA_EXT_SMNPM,
179179
KVM_RISCV_ISA_EXT_SSNPM,
180+
KVM_RISCV_ISA_EXT_SVADE,
181+
KVM_RISCV_ISA_EXT_SVADU,
180182
KVM_RISCV_ISA_EXT_MAX,
181183
};
182184

arch/riscv/kernel/cpufeature.c

Lines changed: 12 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -135,6 +135,16 @@ static int riscv_ext_zcf_validate(const struct riscv_isa_ext_data *data,
135135
return -EPROBE_DEFER;
136136
}
137137

138+
static int riscv_ext_svadu_validate(const struct riscv_isa_ext_data *data,
139+
const unsigned long *isa_bitmap)
140+
{
141+
/* SVADE has already been detected, use SVADE only */
142+
if (__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_SVADE))
143+
return -EOPNOTSUPP;
144+
145+
return 0;
146+
}
147+
138148
static const unsigned int riscv_zk_bundled_exts[] = {
139149
RISCV_ISA_EXT_ZBKB,
140150
RISCV_ISA_EXT_ZBKC,
@@ -386,6 +396,8 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
386396
__RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF),
387397
__RISCV_ISA_EXT_SUPERSET(ssnpm, RISCV_ISA_EXT_SSNPM, riscv_xlinuxenvcfg_exts),
388398
__RISCV_ISA_EXT_DATA(sstc, RISCV_ISA_EXT_SSTC),
399+
__RISCV_ISA_EXT_DATA(svade, RISCV_ISA_EXT_SVADE),
400+
__RISCV_ISA_EXT_DATA_VALIDATE(svadu, RISCV_ISA_EXT_SVADU, riscv_ext_svadu_validate),
389401
__RISCV_ISA_EXT_DATA(svinval, RISCV_ISA_EXT_SVINVAL),
390402
__RISCV_ISA_EXT_DATA(svnapot, RISCV_ISA_EXT_SVNAPOT),
391403
__RISCV_ISA_EXT_DATA(svpbmt, RISCV_ISA_EXT_SVPBMT),

arch/riscv/kvm/vcpu.c

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -551,6 +551,10 @@ static void kvm_riscv_vcpu_setup_config(struct kvm_vcpu *vcpu)
551551
if (riscv_isa_extension_available(isa, ZICBOZ))
552552
cfg->henvcfg |= ENVCFG_CBZE;
553553

554+
if (riscv_isa_extension_available(isa, SVADU) &&
555+
!riscv_isa_extension_available(isa, SVADE))
556+
cfg->henvcfg |= ENVCFG_ADUE;
557+
554558
if (riscv_has_extension_unlikely(RISCV_ISA_EXT_SMSTATEEN)) {
555559
cfg->hstateen0 |= SMSTATEEN0_HSENVCFG;
556560
if (riscv_isa_extension_available(isa, SSAIA))

arch/riscv/kvm/vcpu_onereg.c

Lines changed: 15 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -15,6 +15,7 @@
1515
#include <asm/cacheflush.h>
1616
#include <asm/cpufeature.h>
1717
#include <asm/kvm_vcpu_vector.h>
18+
#include <asm/pgtable.h>
1819
#include <asm/vector.h>
1920

2021
#define KVM_RISCV_BASE_ISA_MASK GENMASK(25, 0)
@@ -40,6 +41,8 @@ static const unsigned long kvm_isa_ext_arr[] = {
4041
KVM_ISA_EXT_ARR(SSCOFPMF),
4142
KVM_ISA_EXT_ARR(SSNPM),
4243
KVM_ISA_EXT_ARR(SSTC),
44+
KVM_ISA_EXT_ARR(SVADE),
45+
KVM_ISA_EXT_ARR(SVADU),
4346
KVM_ISA_EXT_ARR(SVINVAL),
4447
KVM_ISA_EXT_ARR(SVNAPOT),
4548
KVM_ISA_EXT_ARR(SVPBMT),
@@ -112,6 +115,12 @@ static bool kvm_riscv_vcpu_isa_enable_allowed(unsigned long ext)
112115
case KVM_RISCV_ISA_EXT_SSCOFPMF:
113116
/* Sscofpmf depends on interrupt filtering defined in ssaia */
114117
return __riscv_isa_extension_available(NULL, RISCV_ISA_EXT_SSAIA);
118+
case KVM_RISCV_ISA_EXT_SVADU:
119+
/*
120+
* The henvcfg.ADUE is read-only zero if menvcfg.ADUE is zero.
121+
* Guest OS can use Svadu only when host OS enable Svadu.
122+
*/
123+
return arch_has_hw_pte_young();
115124
case KVM_RISCV_ISA_EXT_V:
116125
return riscv_v_vstate_ctrl_user_allowed();
117126
default:
@@ -185,6 +194,12 @@ static bool kvm_riscv_vcpu_isa_disable_allowed(unsigned long ext)
185194
/* Extensions which can be disabled using Smstateen */
186195
case KVM_RISCV_ISA_EXT_SSAIA:
187196
return riscv_has_extension_unlikely(RISCV_ISA_EXT_SMSTATEEN);
197+
case KVM_RISCV_ISA_EXT_SVADE:
198+
/*
199+
* The henvcfg.ADUE is read-only zero if menvcfg.ADUE is zero.
200+
* Svade is not allowed to disable when the platform use Svade.
201+
*/
202+
return arch_has_hw_pte_young();
188203
default:
189204
break;
190205
}

tools/testing/selftests/kvm/riscv/get-reg-list.c

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -47,6 +47,8 @@ bool filter_reg(__u64 reg)
4747
case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SSCOFPMF:
4848
case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SSNPM:
4949
case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SSTC:
50+
case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SVADE:
51+
case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SVADU:
5052
case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SVINVAL:
5153
case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SVNAPOT:
5254
case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SVPBMT:
@@ -422,6 +424,8 @@ static const char *isa_ext_single_id_to_str(__u64 reg_off)
422424
KVM_ISA_EXT_ARR(SSCOFPMF),
423425
KVM_ISA_EXT_ARR(SSNPM),
424426
KVM_ISA_EXT_ARR(SSTC),
427+
KVM_ISA_EXT_ARR(SVADE),
428+
KVM_ISA_EXT_ARR(SVADU),
425429
KVM_ISA_EXT_ARR(SVINVAL),
426430
KVM_ISA_EXT_ARR(SVNAPOT),
427431
KVM_ISA_EXT_ARR(SVPBMT),
@@ -955,6 +959,8 @@ KVM_ISA_EXT_SUBLIST_CONFIG(smstateen, SMSTATEEN);
955959
KVM_ISA_EXT_SIMPLE_CONFIG(sscofpmf, SSCOFPMF);
956960
KVM_ISA_EXT_SIMPLE_CONFIG(ssnpm, SSNPM);
957961
KVM_ISA_EXT_SIMPLE_CONFIG(sstc, SSTC);
962+
KVM_ISA_EXT_SIMPLE_CONFIG(svade, SVADE);
963+
KVM_ISA_EXT_SIMPLE_CONFIG(svadu, SVADU);
958964
KVM_ISA_EXT_SIMPLE_CONFIG(svinval, SVINVAL);
959965
KVM_ISA_EXT_SIMPLE_CONFIG(svnapot, SVNAPOT);
960966
KVM_ISA_EXT_SIMPLE_CONFIG(svpbmt, SVPBMT);
@@ -1020,6 +1026,8 @@ struct vcpu_reg_list *vcpu_configs[] = {
10201026
&config_sscofpmf,
10211027
&config_ssnpm,
10221028
&config_sstc,
1029+
&config_svade,
1030+
&config_svadu,
10231031
&config_svinval,
10241032
&config_svnapot,
10251033
&config_svpbmt,

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