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Merge tag 'riscv-mw2-6.15-rc1' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/alexghiti/linux into for-next
riscv patches for 6.15-rc1, part 2 * A bunch of fixes: - 2 fixes in the purgatory code which prevented kexec to work - Workaround an issue with gcc-15 * tag 'riscv-mw2-6.15-rc1' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/alexghiti/linux: riscv: Add norvc after .option arch in runtime const riscv: Make sure toolchain supports zba before using zba instructions riscv/purgatory: 4B align purgatory_start riscv/kexec_file: Handle R_RISCV_64 in purgatory relocator selftests: riscv: fix v_exec_initval_nolibc.c riscv: Fix hugetlb retrieval of number of ptes in case of !present pte riscv: print hartid on bringup dt-bindings: riscv: document vector crypto requirements dt-bindings: riscv: add vector sub-extension dependencies dt-bindings: riscv: d requires f RISC-V: add f & d extension validation checks RISC-V: add vector crypto extension validation checks RISC-V: add vector extension validation checks
2 parents 95c18b7 + 6ee9281 commit 3eb6409

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lines changed

11 files changed

+260
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lines changed

‎Documentation/devicetree/bindings/riscv/extensions.yaml

Lines changed: 85 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -669,6 +669,12 @@ properties:
669669
https://github.com/T-head-Semi/thead-extension-spec/blob/95358cb2cca9489361c61d335e03d3134b14133f/xtheadvector.adoc.
670670

671671
allOf:
672+
- if:
673+
contains:
674+
const: d
675+
then:
676+
contains:
677+
const: f
672678
# Zcb depends on Zca
673679
- if:
674680
contains:
@@ -738,6 +744,85 @@ properties:
738744
contains:
739745
const: zaamo
740746

747+
- if:
748+
contains:
749+
const: zve32x
750+
then:
751+
contains:
752+
const: zicsr
753+
754+
- if:
755+
contains:
756+
const: zve32f
757+
then:
758+
allOf:
759+
- contains:
760+
const: f
761+
- contains:
762+
const: zve32x
763+
764+
- if:
765+
contains:
766+
const: zve64x
767+
then:
768+
contains:
769+
const: zve32x
770+
771+
- if:
772+
contains:
773+
const: zve64f
774+
then:
775+
allOf:
776+
- contains:
777+
const: f
778+
- contains:
779+
const: zve32f
780+
- contains:
781+
const: zve64x
782+
783+
- if:
784+
contains:
785+
const: zve64d
786+
then:
787+
allOf:
788+
- contains:
789+
const: d
790+
- contains:
791+
const: zve64f
792+
793+
- if:
794+
contains:
795+
anyOf:
796+
- const: zvbc
797+
- const: zvkn
798+
- const: zvknc
799+
- const: zvkng
800+
- const: zvknhb
801+
- const: zvksc
802+
then:
803+
contains:
804+
anyOf:
805+
- const: v
806+
- const: zve64x
807+
808+
- if:
809+
contains:
810+
anyOf:
811+
- const: zvbb
812+
- const: zvkb
813+
- const: zvkg
814+
- const: zvkned
815+
- const: zvknha
816+
- const: zvksed
817+
- const: zvksh
818+
- const: zvks
819+
- const: zvkt
820+
then:
821+
contains:
822+
anyOf:
823+
- const: v
824+
- const: zve32x
825+
741826
allOf:
742827
# Zcf extension does not exist on rv64
743828
- if:

‎arch/riscv/Kconfig

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -729,6 +729,14 @@ config TOOLCHAIN_HAS_VECTOR_CRYPTO
729729
def_bool $(as-instr, .option arch$(comma) +v$(comma) +zvkb)
730730
depends on AS_HAS_OPTION_ARCH
731731

732+
config TOOLCHAIN_HAS_ZBA
733+
bool
734+
default y
735+
depends on !64BIT || $(cc-option,-mabi=lp64 -march=rv64ima_zba)
736+
depends on !32BIT || $(cc-option,-mabi=ilp32 -march=rv32ima_zba)
737+
depends on LLD_VERSION >= 150000 || LD_VERSION >= 23900
738+
depends on AS_HAS_OPTION_ARCH
739+
732740
config RISCV_ISA_ZBA
733741
bool "Zba extension support for bit manipulation instructions"
734742
default y

‎arch/riscv/include/asm/cpufeature.h

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -56,6 +56,9 @@ void __init riscv_user_isa_enable(void);
5656
#define __RISCV_ISA_EXT_BUNDLE(_name, _bundled_exts) \
5757
_RISCV_ISA_EXT_DATA(_name, RISCV_ISA_EXT_INVALID, _bundled_exts, \
5858
ARRAY_SIZE(_bundled_exts), NULL)
59+
#define __RISCV_ISA_EXT_BUNDLE_VALIDATE(_name, _bundled_exts, _validate) \
60+
_RISCV_ISA_EXT_DATA(_name, RISCV_ISA_EXT_INVALID, _bundled_exts, \
61+
ARRAY_SIZE(_bundled_exts), _validate)
5962

6063
/* Used to declare extensions that are a superset of other extensions (Zvbb for instance) */
6164
#define __RISCV_ISA_EXT_SUPERSET(_name, _id, _sub_exts) \

‎arch/riscv/include/asm/runtime-const.h

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -79,7 +79,8 @@
7979
".long 1b - .\n\t" \
8080
".popsection" \
8181

82-
#if defined(CONFIG_RISCV_ISA_ZBA) && defined(CONFIG_RISCV_ISA_ZBKB)
82+
#if defined(CONFIG_RISCV_ISA_ZBA) && defined(CONFIG_TOOLCHAIN_HAS_ZBA) \
83+
&& defined(CONFIG_RISCV_ISA_ZBKB)
8384
#define runtime_const_ptr(sym) \
8485
({ \
8586
typeof(sym) __ret, __tmp; \
@@ -95,7 +96,7 @@
9596
: [__ret] "=r" (__ret), [__tmp] "=r" (__tmp)); \
9697
__ret; \
9798
})
98-
#elif defined(CONFIG_RISCV_ISA_ZBA)
99+
#elif defined(CONFIG_RISCV_ISA_ZBA) && defined(CONFIG_TOOLCHAIN_HAS_ZBA)
99100
#define runtime_const_ptr(sym) \
100101
({ \
101102
typeof(sym) __ret, __tmp; \

‎arch/riscv/kernel/cpufeature.c

Lines changed: 103 additions & 40 deletions
Original file line numberDiff line numberDiff line change
@@ -119,6 +119,82 @@ static int riscv_ext_zicboz_validate(const struct riscv_isa_ext_data *data,
119119
return 0;
120120
}
121121

122+
static int riscv_ext_f_validate(const struct riscv_isa_ext_data *data,
123+
const unsigned long *isa_bitmap)
124+
{
125+
if (!IS_ENABLED(CONFIG_FPU))
126+
return -EINVAL;
127+
128+
/*
129+
* Due to extension ordering, d is checked before f, so no deferral
130+
* is required.
131+
*/
132+
if (!__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_d)) {
133+
pr_warn_once("This kernel does not support systems with F but not D\n");
134+
return -EINVAL;
135+
}
136+
137+
return 0;
138+
}
139+
140+
static int riscv_ext_d_validate(const struct riscv_isa_ext_data *data,
141+
const unsigned long *isa_bitmap)
142+
{
143+
if (!IS_ENABLED(CONFIG_FPU))
144+
return -EINVAL;
145+
146+
return 0;
147+
}
148+
149+
static int riscv_ext_vector_x_validate(const struct riscv_isa_ext_data *data,
150+
const unsigned long *isa_bitmap)
151+
{
152+
if (!IS_ENABLED(CONFIG_RISCV_ISA_V))
153+
return -EINVAL;
154+
155+
return 0;
156+
}
157+
158+
static int riscv_ext_vector_float_validate(const struct riscv_isa_ext_data *data,
159+
const unsigned long *isa_bitmap)
160+
{
161+
if (!IS_ENABLED(CONFIG_RISCV_ISA_V))
162+
return -EINVAL;
163+
164+
if (!IS_ENABLED(CONFIG_FPU))
165+
return -EINVAL;
166+
167+
/*
168+
* The kernel doesn't support systems that don't implement both of
169+
* F and D, so if any of the vector extensions that do floating point
170+
* are to be usable, both floating point extensions need to be usable.
171+
*
172+
* Since this function validates vector only, and v/Zve* are probed
173+
* after f/d, there's no need for a deferral here.
174+
*/
175+
if (!__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_d))
176+
return -EINVAL;
177+
178+
return 0;
179+
}
180+
181+
static int riscv_ext_vector_crypto_validate(const struct riscv_isa_ext_data *data,
182+
const unsigned long *isa_bitmap)
183+
{
184+
if (!IS_ENABLED(CONFIG_RISCV_ISA_V))
185+
return -EINVAL;
186+
187+
/*
188+
* It isn't the kernel's job to check that the binding is correct, so
189+
* it should be enough to check that any of the vector extensions are
190+
* enabled, which in-turn means that vector is usable in this kernel
191+
*/
192+
if (!__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_ZVE32X))
193+
return -EPROBE_DEFER;
194+
195+
return 0;
196+
}
197+
122198
static int riscv_ext_zca_depends(const struct riscv_isa_ext_data *data,
123199
const unsigned long *isa_bitmap)
124200
{
@@ -359,16 +435,14 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
359435
__RISCV_ISA_EXT_DATA(i, RISCV_ISA_EXT_i),
360436
__RISCV_ISA_EXT_DATA(m, RISCV_ISA_EXT_m),
361437
__RISCV_ISA_EXT_SUPERSET(a, RISCV_ISA_EXT_a, riscv_a_exts),
362-
__RISCV_ISA_EXT_DATA(f, RISCV_ISA_EXT_f),
363-
__RISCV_ISA_EXT_DATA(d, RISCV_ISA_EXT_d),
438+
__RISCV_ISA_EXT_DATA_VALIDATE(f, RISCV_ISA_EXT_f, riscv_ext_f_validate),
439+
__RISCV_ISA_EXT_DATA_VALIDATE(d, RISCV_ISA_EXT_d, riscv_ext_d_validate),
364440
__RISCV_ISA_EXT_DATA(q, RISCV_ISA_EXT_q),
365441
__RISCV_ISA_EXT_SUPERSET(c, RISCV_ISA_EXT_c, riscv_c_exts),
366-
__RISCV_ISA_EXT_SUPERSET(v, RISCV_ISA_EXT_v, riscv_v_exts),
442+
__RISCV_ISA_EXT_SUPERSET_VALIDATE(v, RISCV_ISA_EXT_v, riscv_v_exts, riscv_ext_vector_float_validate),
367443
__RISCV_ISA_EXT_DATA(h, RISCV_ISA_EXT_h),
368-
__RISCV_ISA_EXT_SUPERSET_VALIDATE(zicbom, RISCV_ISA_EXT_ZICBOM, riscv_xlinuxenvcfg_exts,
369-
riscv_ext_zicbom_validate),
370-
__RISCV_ISA_EXT_SUPERSET_VALIDATE(zicboz, RISCV_ISA_EXT_ZICBOZ, riscv_xlinuxenvcfg_exts,
371-
riscv_ext_zicboz_validate),
444+
__RISCV_ISA_EXT_SUPERSET_VALIDATE(zicbom, RISCV_ISA_EXT_ZICBOM, riscv_xlinuxenvcfg_exts, riscv_ext_zicbom_validate),
445+
__RISCV_ISA_EXT_SUPERSET_VALIDATE(zicboz, RISCV_ISA_EXT_ZICBOZ, riscv_xlinuxenvcfg_exts, riscv_ext_zicboz_validate),
372446
__RISCV_ISA_EXT_DATA(ziccrse, RISCV_ISA_EXT_ZICCRSE),
373447
__RISCV_ISA_EXT_DATA(zicntr, RISCV_ISA_EXT_ZICNTR),
374448
__RISCV_ISA_EXT_DATA(zicond, RISCV_ISA_EXT_ZICOND),
@@ -410,32 +484,31 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
410484
__RISCV_ISA_EXT_DATA(zksed, RISCV_ISA_EXT_ZKSED),
411485
__RISCV_ISA_EXT_DATA(zksh, RISCV_ISA_EXT_ZKSH),
412486
__RISCV_ISA_EXT_DATA(ztso, RISCV_ISA_EXT_ZTSO),
413-
__RISCV_ISA_EXT_SUPERSET(zvbb, RISCV_ISA_EXT_ZVBB, riscv_zvbb_exts),
414-
__RISCV_ISA_EXT_DATA(zvbc, RISCV_ISA_EXT_ZVBC),
415-
__RISCV_ISA_EXT_SUPERSET(zve32f, RISCV_ISA_EXT_ZVE32F, riscv_zve32f_exts),
416-
__RISCV_ISA_EXT_DATA(zve32x, RISCV_ISA_EXT_ZVE32X),
417-
__RISCV_ISA_EXT_SUPERSET(zve64d, RISCV_ISA_EXT_ZVE64D, riscv_zve64d_exts),
418-
__RISCV_ISA_EXT_SUPERSET(zve64f, RISCV_ISA_EXT_ZVE64F, riscv_zve64f_exts),
419-
__RISCV_ISA_EXT_SUPERSET(zve64x, RISCV_ISA_EXT_ZVE64X, riscv_zve64x_exts),
487+
__RISCV_ISA_EXT_SUPERSET_VALIDATE(zvbb, RISCV_ISA_EXT_ZVBB, riscv_zvbb_exts, riscv_ext_vector_crypto_validate),
488+
__RISCV_ISA_EXT_DATA_VALIDATE(zvbc, RISCV_ISA_EXT_ZVBC, riscv_ext_vector_crypto_validate),
489+
__RISCV_ISA_EXT_SUPERSET_VALIDATE(zve32f, RISCV_ISA_EXT_ZVE32F, riscv_zve32f_exts, riscv_ext_vector_float_validate),
490+
__RISCV_ISA_EXT_DATA_VALIDATE(zve32x, RISCV_ISA_EXT_ZVE32X, riscv_ext_vector_x_validate),
491+
__RISCV_ISA_EXT_SUPERSET_VALIDATE(zve64d, RISCV_ISA_EXT_ZVE64D, riscv_zve64d_exts, riscv_ext_vector_float_validate),
492+
__RISCV_ISA_EXT_SUPERSET_VALIDATE(zve64f, RISCV_ISA_EXT_ZVE64F, riscv_zve64f_exts, riscv_ext_vector_float_validate),
493+
__RISCV_ISA_EXT_SUPERSET_VALIDATE(zve64x, RISCV_ISA_EXT_ZVE64X, riscv_zve64x_exts, riscv_ext_vector_x_validate),
420494
__RISCV_ISA_EXT_DATA_VALIDATE(zvfbfmin, RISCV_ISA_EXT_ZVFBFMIN, riscv_vector_f_validate),
421-
__RISCV_ISA_EXT_DATA_VALIDATE(zvfbfwma, RISCV_ISA_EXT_ZVFBFWMA,
422-
riscv_ext_zvfbfwma_validate),
495+
__RISCV_ISA_EXT_DATA_VALIDATE(zvfbfwma, RISCV_ISA_EXT_ZVFBFWMA, riscv_ext_zvfbfwma_validate),
423496
__RISCV_ISA_EXT_DATA(zvfh, RISCV_ISA_EXT_ZVFH),
424497
__RISCV_ISA_EXT_DATA(zvfhmin, RISCV_ISA_EXT_ZVFHMIN),
425-
__RISCV_ISA_EXT_DATA(zvkb, RISCV_ISA_EXT_ZVKB),
426-
__RISCV_ISA_EXT_DATA(zvkg, RISCV_ISA_EXT_ZVKG),
427-
__RISCV_ISA_EXT_BUNDLE(zvkn, riscv_zvkn_bundled_exts),
428-
__RISCV_ISA_EXT_BUNDLE(zvknc, riscv_zvknc_bundled_exts),
429-
__RISCV_ISA_EXT_DATA(zvkned, RISCV_ISA_EXT_ZVKNED),
430-
__RISCV_ISA_EXT_BUNDLE(zvkng, riscv_zvkng_bundled_exts),
431-
__RISCV_ISA_EXT_DATA(zvknha, RISCV_ISA_EXT_ZVKNHA),
432-
__RISCV_ISA_EXT_DATA(zvknhb, RISCV_ISA_EXT_ZVKNHB),
433-
__RISCV_ISA_EXT_BUNDLE(zvks, riscv_zvks_bundled_exts),
434-
__RISCV_ISA_EXT_BUNDLE(zvksc, riscv_zvksc_bundled_exts),
435-
__RISCV_ISA_EXT_DATA(zvksed, RISCV_ISA_EXT_ZVKSED),
436-
__RISCV_ISA_EXT_DATA(zvksh, RISCV_ISA_EXT_ZVKSH),
437-
__RISCV_ISA_EXT_BUNDLE(zvksg, riscv_zvksg_bundled_exts),
438-
__RISCV_ISA_EXT_DATA(zvkt, RISCV_ISA_EXT_ZVKT),
498+
__RISCV_ISA_EXT_DATA_VALIDATE(zvkb, RISCV_ISA_EXT_ZVKB, riscv_ext_vector_crypto_validate),
499+
__RISCV_ISA_EXT_DATA_VALIDATE(zvkg, RISCV_ISA_EXT_ZVKG, riscv_ext_vector_crypto_validate),
500+
__RISCV_ISA_EXT_BUNDLE_VALIDATE(zvkn, riscv_zvkn_bundled_exts, riscv_ext_vector_crypto_validate),
501+
__RISCV_ISA_EXT_BUNDLE_VALIDATE(zvknc, riscv_zvknc_bundled_exts, riscv_ext_vector_crypto_validate),
502+
__RISCV_ISA_EXT_DATA_VALIDATE(zvkned, RISCV_ISA_EXT_ZVKNED, riscv_ext_vector_crypto_validate),
503+
__RISCV_ISA_EXT_BUNDLE_VALIDATE(zvkng, riscv_zvkng_bundled_exts, riscv_ext_vector_crypto_validate),
504+
__RISCV_ISA_EXT_DATA_VALIDATE(zvknha, RISCV_ISA_EXT_ZVKNHA, riscv_ext_vector_crypto_validate),
505+
__RISCV_ISA_EXT_DATA_VALIDATE(zvknhb, RISCV_ISA_EXT_ZVKNHB, riscv_ext_vector_crypto_validate),
506+
__RISCV_ISA_EXT_BUNDLE_VALIDATE(zvks, riscv_zvks_bundled_exts, riscv_ext_vector_crypto_validate),
507+
__RISCV_ISA_EXT_BUNDLE_VALIDATE(zvksc, riscv_zvksc_bundled_exts, riscv_ext_vector_crypto_validate),
508+
__RISCV_ISA_EXT_DATA_VALIDATE(zvksed, RISCV_ISA_EXT_ZVKSED, riscv_ext_vector_crypto_validate),
509+
__RISCV_ISA_EXT_DATA_VALIDATE(zvksh, RISCV_ISA_EXT_ZVKSH, riscv_ext_vector_crypto_validate),
510+
__RISCV_ISA_EXT_BUNDLE_VALIDATE(zvksg, riscv_zvksg_bundled_exts, riscv_ext_vector_crypto_validate),
511+
__RISCV_ISA_EXT_DATA_VALIDATE(zvkt, RISCV_ISA_EXT_ZVKT, riscv_ext_vector_crypto_validate),
439512
__RISCV_ISA_EXT_DATA(smaia, RISCV_ISA_EXT_SMAIA),
440513
__RISCV_ISA_EXT_DATA(smmpm, RISCV_ISA_EXT_SMMPM),
441514
__RISCV_ISA_EXT_SUPERSET(smnpm, RISCV_ISA_EXT_SMNPM, riscv_xlinuxenvcfg_exts),
@@ -1003,16 +1076,6 @@ void __init riscv_fill_hwcap(void)
10031076
riscv_v_setup_vsize();
10041077
}
10051078

1006-
if (elf_hwcap & COMPAT_HWCAP_ISA_V) {
1007-
/*
1008-
* ISA string in device tree might have 'v' flag, but
1009-
* CONFIG_RISCV_ISA_V is disabled in kernel.
1010-
* Clear V flag in elf_hwcap if CONFIG_RISCV_ISA_V is disabled.
1011-
*/
1012-
if (!IS_ENABLED(CONFIG_RISCV_ISA_V))
1013-
elf_hwcap &= ~COMPAT_HWCAP_ISA_V;
1014-
}
1015-
10161079
memset(print_str, 0, sizeof(print_str));
10171080
for (i = 0, j = 0; i < NUM_ALPHA_EXTS; i++)
10181081
if (riscv_isa[0] & BIT_MASK(i))

‎arch/riscv/kernel/elf_kexec.c

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -468,6 +468,9 @@ int arch_kexec_apply_relocations_add(struct purgatory_info *pi,
468468
case R_RISCV_ALIGN:
469469
case R_RISCV_RELAX:
470470
break;
471+
case R_RISCV_64:
472+
*(u64 *)loc = val;
473+
break;
471474
default:
472475
pr_err("Unknown rela relocation: %d\n", r_type);
473476
return -ENOEXEC;

‎arch/riscv/kernel/smp.c

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -48,6 +48,8 @@ EXPORT_SYMBOL_GPL(__cpuid_to_hartid_map);
4848
void __init smp_setup_processor_id(void)
4949
{
5050
cpuid_to_hartid_map(0) = boot_cpu_hartid;
51+
52+
pr_info("Booting Linux on hartid %lu\n", boot_cpu_hartid);
5153
}
5254

5355
static DEFINE_PER_CPU_READ_MOSTLY(int, ipi_dummy_dev);

‎arch/riscv/kernel/smpboot.c

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -231,6 +231,10 @@ asmlinkage __visible void smp_callin(void)
231231
riscv_ipi_enable();
232232

233233
numa_add_cpu(curr_cpuid);
234+
235+
pr_debug("CPU%u: Booted secondary hartid %lu\n", curr_cpuid,
236+
cpuid_to_hartid_map(curr_cpuid));
237+
234238
set_cpu_online(curr_cpuid, true);
235239

236240
/*

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