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geertugeertu
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pinctrl: renesas: r8a779g0: Fix TPU suffixes
The Timer Pulse Unit channels have two alternate pin groups: "tpu_to[0-3]" and "tpu_to[0-3]_a". Increase uniformity by adopting R-Car V4M naming: - Rename "tpu_to[0-3]_a" to "tpu_to[0-3]_b", - Rename "tpu_to[0-3]" to "tpu_to[0-3]_a", Fixes: ad9bb2f ("pinctrl: renesas: Initial R8A779G0 (R-Car V4H) PFC support") Fixes: 050442a ("pinctrl: renesas: r8a779g0: Add pins, groups and functions") Fixes: 85a9cbe ("pinctrl: renesas: r8a779g0: Add missing TPU0TOx_A") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/0dd9428bc24e97e1001ed3976b1cb98966f5e7e3.1717754960.git.geert+renesas@glider.be
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‎drivers/pinctrl/renesas/pfc-r8a779g0.c

Lines changed: 63 additions & 65 deletions
Original file line numberDiff line numberDiff line change
@@ -119,8 +119,8 @@
119119
#define GPSR2_11 F_(CANFD0_RX, IP1SR2_15_12)
120120
#define GPSR2_10 F_(CANFD0_TX, IP1SR2_11_8)
121121
#define GPSR2_9 F_(CAN_CLK, IP1SR2_7_4)
122-
#define GPSR2_8 F_(TPU0TO0, IP1SR2_3_0)
123-
#define GPSR2_7 F_(TPU0TO1, IP0SR2_31_28)
122+
#define GPSR2_8 F_(TPU0TO0_A, IP1SR2_3_0)
123+
#define GPSR2_7 F_(TPU0TO1_A, IP0SR2_31_28)
124124
#define GPSR2_6 F_(FXR_TXDB, IP0SR2_27_24)
125125
#define GPSR2_5 F_(FXR_TXENB_N_A, IP0SR2_23_20)
126126
#define GPSR2_4 F_(RXDB_EXTFXR, IP0SR2_19_16)
@@ -332,29 +332,29 @@
332332

333333
/* IP3SR1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
334334
#define IP3SR1_3_0 FM(HRX3_A) FM(SCK3_A) FM(MSIOF4_SS2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
335-
#define IP3SR1_7_4 FM(HSCK3_A) FM(CTS3_N_A) FM(MSIOF4_SCK) FM(TPU0TO0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
336-
#define IP3SR1_11_8 FM(HRTS3_N_A) FM(RTS3_N_A) FM(MSIOF4_TXD) FM(TPU0TO1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
335+
#define IP3SR1_7_4 FM(HSCK3_A) FM(CTS3_N_A) FM(MSIOF4_SCK) FM(TPU0TO0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
336+
#define IP3SR1_11_8 FM(HRTS3_N_A) FM(RTS3_N_A) FM(MSIOF4_TXD) FM(TPU0TO1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
337337
#define IP3SR1_15_12 FM(HCTS3_N_A) FM(RX3_A) FM(MSIOF4_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
338338
#define IP3SR1_19_16 FM(HTX3_A) FM(TX3_A) FM(MSIOF4_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
339339

340340
/* SR2 */
341341
/* IP0SR2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
342-
#define IP0SR2_3_0 FM(FXR_TXDA) FM(CANFD1_TX) FM(TPU0TO2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
343-
#define IP0SR2_7_4 FM(FXR_TXENA_N_A) FM(CANFD1_RX) FM(TPU0TO3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
342+
#define IP0SR2_3_0 FM(FXR_TXDA) FM(CANFD1_TX) FM(TPU0TO2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
343+
#define IP0SR2_7_4 FM(FXR_TXENA_N_A) FM(CANFD1_RX) FM(TPU0TO3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
344344
#define IP0SR2_11_8 FM(RXDA_EXTFXR) FM(CANFD5_TX_A) FM(IRQ5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
345345
#define IP0SR2_15_12 FM(CLK_EXTFXR) FM(CANFD5_RX_A) FM(IRQ4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
346346
#define IP0SR2_19_16 FM(RXDB_EXTFXR) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
347347
#define IP0SR2_23_20 FM(FXR_TXENB_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
348348
#define IP0SR2_27_24 FM(FXR_TXDB) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
349-
#define IP0SR2_31_28 FM(TPU0TO1) FM(CANFD6_TX) F_(0, 0) FM(TCLK2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
349+
#define IP0SR2_31_28 FM(TPU0TO1_A) FM(CANFD6_TX) F_(0, 0) FM(TCLK2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
350350

351351
/* IP1SR2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
352-
#define IP1SR2_3_0 FM(TPU0TO0) FM(CANFD6_RX) F_(0, 0) FM(TCLK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
352+
#define IP1SR2_3_0 FM(TPU0TO0_A) FM(CANFD6_RX) F_(0, 0) FM(TCLK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
353353
#define IP1SR2_7_4 FM(CAN_CLK) FM(FXR_TXENA_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
354354
#define IP1SR2_11_8 FM(CANFD0_TX) FM(FXR_TXENB_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
355355
#define IP1SR2_15_12 FM(CANFD0_RX) FM(STPWT_EXTFXR) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
356-
#define IP1SR2_19_16 FM(CANFD2_TX) FM(TPU0TO2) F_(0, 0) FM(TCLK3_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
357-
#define IP1SR2_23_20 FM(CANFD2_RX) FM(TPU0TO3) FM(PWM1_B) FM(TCLK4_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
356+
#define IP1SR2_19_16 FM(CANFD2_TX) FM(TPU0TO2_A) F_(0, 0) FM(TCLK3_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
357+
#define IP1SR2_23_20 FM(CANFD2_RX) FM(TPU0TO3_A) FM(PWM1_B) FM(TCLK4_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
358358
#define IP1SR2_27_24 FM(CANFD3_TX) F_(0, 0) FM(PWM2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
359359
#define IP1SR2_31_28 FM(CANFD3_RX) F_(0, 0) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
360360

@@ -871,12 +871,12 @@ static const u16 pinmux_data[] = {
871871
PINMUX_IPSR_GPSR(IP3SR1_7_4, HSCK3_A),
872872
PINMUX_IPSR_GPSR(IP3SR1_7_4, CTS3_N_A),
873873
PINMUX_IPSR_GPSR(IP3SR1_7_4, MSIOF4_SCK),
874-
PINMUX_IPSR_GPSR(IP3SR1_7_4, TPU0TO0_A),
874+
PINMUX_IPSR_GPSR(IP3SR1_7_4, TPU0TO0_B),
875875

876876
PINMUX_IPSR_GPSR(IP3SR1_11_8, HRTS3_N_A),
877877
PINMUX_IPSR_GPSR(IP3SR1_11_8, RTS3_N_A),
878878
PINMUX_IPSR_GPSR(IP3SR1_11_8, MSIOF4_TXD),
879-
PINMUX_IPSR_GPSR(IP3SR1_11_8, TPU0TO1_A),
879+
PINMUX_IPSR_GPSR(IP3SR1_11_8, TPU0TO1_B),
880880

881881
PINMUX_IPSR_GPSR(IP3SR1_15_12, HCTS3_N_A),
882882
PINMUX_IPSR_GPSR(IP3SR1_15_12, RX3_A),
@@ -889,11 +889,11 @@ static const u16 pinmux_data[] = {
889889
/* IP0SR2 */
890890
PINMUX_IPSR_GPSR(IP0SR2_3_0, FXR_TXDA),
891891
PINMUX_IPSR_GPSR(IP0SR2_3_0, CANFD1_TX),
892-
PINMUX_IPSR_GPSR(IP0SR2_3_0, TPU0TO2_A),
892+
PINMUX_IPSR_GPSR(IP0SR2_3_0, TPU0TO2_B),
893893

894894
PINMUX_IPSR_GPSR(IP0SR2_7_4, FXR_TXENA_N_A),
895895
PINMUX_IPSR_GPSR(IP0SR2_7_4, CANFD1_RX),
896-
PINMUX_IPSR_GPSR(IP0SR2_7_4, TPU0TO3_A),
896+
PINMUX_IPSR_GPSR(IP0SR2_7_4, TPU0TO3_B),
897897

898898
PINMUX_IPSR_GPSR(IP0SR2_11_8, RXDA_EXTFXR),
899899
PINMUX_IPSR_GPSR(IP0SR2_11_8, CANFD5_TX_A),
@@ -909,12 +909,12 @@ static const u16 pinmux_data[] = {
909909

910910
PINMUX_IPSR_GPSR(IP0SR2_27_24, FXR_TXDB),
911911

912-
PINMUX_IPSR_GPSR(IP0SR2_31_28, TPU0TO1),
912+
PINMUX_IPSR_GPSR(IP0SR2_31_28, TPU0TO1_A),
913913
PINMUX_IPSR_GPSR(IP0SR2_31_28, CANFD6_TX),
914914
PINMUX_IPSR_GPSR(IP0SR2_31_28, TCLK2_C),
915915

916916
/* IP1SR2 */
917-
PINMUX_IPSR_GPSR(IP1SR2_3_0, TPU0TO0),
917+
PINMUX_IPSR_GPSR(IP1SR2_3_0, TPU0TO0_A),
918918
PINMUX_IPSR_GPSR(IP1SR2_3_0, CANFD6_RX),
919919
PINMUX_IPSR_GPSR(IP1SR2_3_0, TCLK1_B),
920920

@@ -928,11 +928,11 @@ static const u16 pinmux_data[] = {
928928
PINMUX_IPSR_GPSR(IP1SR2_15_12, STPWT_EXTFXR),
929929

930930
PINMUX_IPSR_GPSR(IP1SR2_19_16, CANFD2_TX),
931-
PINMUX_IPSR_GPSR(IP1SR2_19_16, TPU0TO2),
931+
PINMUX_IPSR_GPSR(IP1SR2_19_16, TPU0TO2_A),
932932
PINMUX_IPSR_GPSR(IP1SR2_19_16, TCLK3_C),
933933

934934
PINMUX_IPSR_GPSR(IP1SR2_23_20, CANFD2_RX),
935-
PINMUX_IPSR_GPSR(IP1SR2_23_20, TPU0TO3),
935+
PINMUX_IPSR_GPSR(IP1SR2_23_20, TPU0TO3_A),
936936
PINMUX_IPSR_GPSR(IP1SR2_23_20, PWM1_B),
937937
PINMUX_IPSR_GPSR(IP1SR2_23_20, TCLK4_C),
938938

@@ -2403,64 +2403,63 @@ static const unsigned int ssi_ctrl_mux[] = {
24032403
SSI_SCK_MARK, SSI_WS_MARK,
24042404
};
24052405

2406-
/* - TPU ------------------------------------------------------------------- */
2407-
static const unsigned int tpu_to0_pins[] = {
2408-
/* TPU0TO0 */
2406+
/* - TPU -------------------------------------------------------------------- */
2407+
static const unsigned int tpu_to0_a_pins[] = {
2408+
/* TPU0TO0_A */
24092409
RCAR_GP_PIN(2, 8),
24102410
};
2411-
static const unsigned int tpu_to0_mux[] = {
2412-
TPU0TO0_MARK,
2411+
static const unsigned int tpu_to0_a_mux[] = {
2412+
TPU0TO0_A_MARK,
24132413
};
2414-
static const unsigned int tpu_to1_pins[] = {
2415-
/* TPU0TO1 */
2414+
static const unsigned int tpu_to1_a_pins[] = {
2415+
/* TPU0TO1_A */
24162416
RCAR_GP_PIN(2, 7),
24172417
};
2418-
static const unsigned int tpu_to1_mux[] = {
2419-
TPU0TO1_MARK,
2418+
static const unsigned int tpu_to1_a_mux[] = {
2419+
TPU0TO1_A_MARK,
24202420
};
2421-
static const unsigned int tpu_to2_pins[] = {
2422-
/* TPU0TO2 */
2421+
static const unsigned int tpu_to2_a_pins[] = {
2422+
/* TPU0TO2_A */
24232423
RCAR_GP_PIN(2, 12),
24242424
};
2425-
static const unsigned int tpu_to2_mux[] = {
2426-
TPU0TO2_MARK,
2425+
static const unsigned int tpu_to2_a_mux[] = {
2426+
TPU0TO2_A_MARK,
24272427
};
2428-
static const unsigned int tpu_to3_pins[] = {
2429-
/* TPU0TO3 */
2428+
static const unsigned int tpu_to3_a_pins[] = {
2429+
/* TPU0TO3_A */
24302430
RCAR_GP_PIN(2, 13),
24312431
};
2432-
static const unsigned int tpu_to3_mux[] = {
2433-
TPU0TO3_MARK,
2432+
static const unsigned int tpu_to3_a_mux[] = {
2433+
TPU0TO3_A_MARK,
24342434
};
24352435

2436-
/* - TPU_A ------------------------------------------------------------------- */
2437-
static const unsigned int tpu_to0_a_pins[] = {
2438-
/* TPU0TO0_A */
2436+
static const unsigned int tpu_to0_b_pins[] = {
2437+
/* TPU0TO0_B */
24392438
RCAR_GP_PIN(1, 25),
24402439
};
2441-
static const unsigned int tpu_to0_a_mux[] = {
2442-
TPU0TO0_A_MARK,
2440+
static const unsigned int tpu_to0_b_mux[] = {
2441+
TPU0TO0_B_MARK,
24432442
};
2444-
static const unsigned int tpu_to1_a_pins[] = {
2445-
/* TPU0TO1_A */
2443+
static const unsigned int tpu_to1_b_pins[] = {
2444+
/* TPU0TO1_B */
24462445
RCAR_GP_PIN(1, 26),
24472446
};
2448-
static const unsigned int tpu_to1_a_mux[] = {
2449-
TPU0TO1_A_MARK,
2447+
static const unsigned int tpu_to1_b_mux[] = {
2448+
TPU0TO1_B_MARK,
24502449
};
2451-
static const unsigned int tpu_to2_a_pins[] = {
2452-
/* TPU0TO2_A */
2450+
static const unsigned int tpu_to2_b_pins[] = {
2451+
/* TPU0TO2_B */
24532452
RCAR_GP_PIN(2, 0),
24542453
};
2455-
static const unsigned int tpu_to2_a_mux[] = {
2456-
TPU0TO2_A_MARK,
2454+
static const unsigned int tpu_to2_b_mux[] = {
2455+
TPU0TO2_B_MARK,
24572456
};
2458-
static const unsigned int tpu_to3_a_pins[] = {
2459-
/* TPU0TO3_A */
2457+
static const unsigned int tpu_to3_b_pins[] = {
2458+
/* TPU0TO3_B */
24602459
RCAR_GP_PIN(2, 1),
24612460
};
2462-
static const unsigned int tpu_to3_a_mux[] = {
2463-
TPU0TO3_A_MARK,
2461+
static const unsigned int tpu_to3_b_mux[] = {
2462+
TPU0TO3_B_MARK,
24642463
};
24652464

24662465
/* - TSN0 ------------------------------------------------ */
@@ -2702,14 +2701,14 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
27022701
SH_PFC_PIN_GROUP(ssi_data),
27032702
SH_PFC_PIN_GROUP(ssi_ctrl),
27042703

2705-
SH_PFC_PIN_GROUP(tpu_to0), /* suffix might be updated */
2706-
SH_PFC_PIN_GROUP(tpu_to0_a), /* suffix might be updated */
2707-
SH_PFC_PIN_GROUP(tpu_to1), /* suffix might be updated */
2708-
SH_PFC_PIN_GROUP(tpu_to1_a), /* suffix might be updated */
2709-
SH_PFC_PIN_GROUP(tpu_to2), /* suffix might be updated */
2710-
SH_PFC_PIN_GROUP(tpu_to2_a), /* suffix might be updated */
2711-
SH_PFC_PIN_GROUP(tpu_to3), /* suffix might be updated */
2712-
SH_PFC_PIN_GROUP(tpu_to3_a), /* suffix might be updated */
2704+
SH_PFC_PIN_GROUP(tpu_to0_a),
2705+
SH_PFC_PIN_GROUP(tpu_to0_b),
2706+
SH_PFC_PIN_GROUP(tpu_to1_a),
2707+
SH_PFC_PIN_GROUP(tpu_to1_b),
2708+
SH_PFC_PIN_GROUP(tpu_to2_a),
2709+
SH_PFC_PIN_GROUP(tpu_to2_b),
2710+
SH_PFC_PIN_GROUP(tpu_to3_a),
2711+
SH_PFC_PIN_GROUP(tpu_to3_b),
27132712

27142713
SH_PFC_PIN_GROUP(tsn0_link),
27152714
SH_PFC_PIN_GROUP(tsn0_phy_int),
@@ -3020,15 +3019,14 @@ static const char * const ssi_groups[] = {
30203019
};
30213020

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static const char * const tpu_groups[] = {
3023-
/* suffix might be updated */
3024-
"tpu_to0",
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"tpu_to0_a",
3026-
"tpu_to1",
3023+
"tpu_to0_b",
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"tpu_to1_a",
3028-
"tpu_to2",
3025+
"tpu_to1_b",
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"tpu_to2_a",
3030-
"tpu_to3",
3027+
"tpu_to2_b",
30313028
"tpu_to3_a",
3029+
"tpu_to3_b",
30323030
};
30333031

30343032
static const char * const tsn0_groups[] = {

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