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davidwuAMDalexdeucher
davidwuAMD
authored and
alexdeucher
committed
drm/amd/amdgpu: apply command submission parser for JPEG v2+
This patch extends the same cs parser from JPEG v4.0.3 to other JPEG versions (v2 and above). Rename to more common name as jpeg_v2_dec_ring_parse_cs() from jpeg_v4_0_3_dec_ring_parse_cs(). Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: David (Ming Qiang) Wu <David.Wu3@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> (cherry picked from commit 88dcad2) Cc: stable@vger.kernel.org
1 parent 7a09825 commit 3a23aa0

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10 files changed

+78
-64
lines changed

10 files changed

+78
-64
lines changed

‎drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c

Lines changed: 62 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -23,6 +23,7 @@
2323

2424
#include "amdgpu.h"
2525
#include "amdgpu_jpeg.h"
26+
#include "amdgpu_cs.h"
2627
#include "amdgpu_pm.h"
2728
#include "soc15.h"
2829
#include "soc15d.h"
@@ -538,7 +539,11 @@ void jpeg_v2_0_dec_ring_emit_ib(struct amdgpu_ring *ring,
538539

539540
amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JRBC_IB_VMID_INTERNAL_OFFSET,
540541
0, 0, PACKETJ_TYPE0));
541-
amdgpu_ring_write(ring, (vmid | (vmid << 4) | (vmid << 8)));
542+
543+
if (ring->funcs->parse_cs)
544+
amdgpu_ring_write(ring, 0);
545+
else
546+
amdgpu_ring_write(ring, (vmid | (vmid << 4) | (vmid << 8)));
542547

543548
amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JPEG_VMID_INTERNAL_OFFSET,
544549
0, 0, PACKETJ_TYPE0));
@@ -764,6 +769,7 @@ static const struct amdgpu_ring_funcs jpeg_v2_0_dec_ring_vm_funcs = {
764769
.get_rptr = jpeg_v2_0_dec_ring_get_rptr,
765770
.get_wptr = jpeg_v2_0_dec_ring_get_wptr,
766771
.set_wptr = jpeg_v2_0_dec_ring_set_wptr,
772+
.parse_cs = jpeg_v2_dec_ring_parse_cs,
767773
.emit_frame_size =
768774
SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
769775
SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +
@@ -810,3 +816,58 @@ const struct amdgpu_ip_block_version jpeg_v2_0_ip_block = {
810816
.rev = 0,
811817
.funcs = &jpeg_v2_0_ip_funcs,
812818
};
819+
820+
/**
821+
* jpeg_v2_dec_ring_parse_cs - command submission parser
822+
*
823+
* @parser: Command submission parser context
824+
* @job: the job to parse
825+
* @ib: the IB to parse
826+
*
827+
* Parse the command stream, return -EINVAL for invalid packet,
828+
* 0 otherwise
829+
*/
830+
int jpeg_v2_dec_ring_parse_cs(struct amdgpu_cs_parser *parser,
831+
struct amdgpu_job *job,
832+
struct amdgpu_ib *ib)
833+
{
834+
u32 i, reg, res, cond, type;
835+
struct amdgpu_device *adev = parser->adev;
836+
837+
for (i = 0; i < ib->length_dw ; i += 2) {
838+
reg = CP_PACKETJ_GET_REG(ib->ptr[i]);
839+
res = CP_PACKETJ_GET_RES(ib->ptr[i]);
840+
cond = CP_PACKETJ_GET_COND(ib->ptr[i]);
841+
type = CP_PACKETJ_GET_TYPE(ib->ptr[i]);
842+
843+
if (res) /* only support 0 at the moment */
844+
return -EINVAL;
845+
846+
switch (type) {
847+
case PACKETJ_TYPE0:
848+
if (cond != PACKETJ_CONDITION_CHECK0 || reg < JPEG_REG_RANGE_START ||
849+
reg > JPEG_REG_RANGE_END) {
850+
dev_err(adev->dev, "Invalid packet [0x%08x]!\n", ib->ptr[i]);
851+
return -EINVAL;
852+
}
853+
break;
854+
case PACKETJ_TYPE3:
855+
if (cond != PACKETJ_CONDITION_CHECK3 || reg < JPEG_REG_RANGE_START ||
856+
reg > JPEG_REG_RANGE_END) {
857+
dev_err(adev->dev, "Invalid packet [0x%08x]!\n", ib->ptr[i]);
858+
return -EINVAL;
859+
}
860+
break;
861+
case PACKETJ_TYPE6:
862+
if (ib->ptr[i] == CP_PACKETJ_NOP)
863+
continue;
864+
dev_err(adev->dev, "Invalid packet [0x%08x]!\n", ib->ptr[i]);
865+
return -EINVAL;
866+
default:
867+
dev_err(adev->dev, "Unknown packet type %d !\n", type);
868+
return -EINVAL;
869+
}
870+
}
871+
872+
return 0;
873+
}

‎drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.h

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -45,6 +45,9 @@
4545

4646
#define JRBC_DEC_EXTERNAL_REG_WRITE_ADDR 0x18000
4747

48+
#define JPEG_REG_RANGE_START 0x4000
49+
#define JPEG_REG_RANGE_END 0x41c2
50+
4851
void jpeg_v2_0_dec_ring_insert_start(struct amdgpu_ring *ring);
4952
void jpeg_v2_0_dec_ring_insert_end(struct amdgpu_ring *ring);
5053
void jpeg_v2_0_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
@@ -57,6 +60,9 @@ void jpeg_v2_0_dec_ring_emit_vm_flush(struct amdgpu_ring *ring,
5760
unsigned vmid, uint64_t pd_addr);
5861
void jpeg_v2_0_dec_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val);
5962
void jpeg_v2_0_dec_ring_nop(struct amdgpu_ring *ring, uint32_t count);
63+
int jpeg_v2_dec_ring_parse_cs(struct amdgpu_cs_parser *parser,
64+
struct amdgpu_job *job,
65+
struct amdgpu_ib *ib);
6066

6167
extern const struct amdgpu_ip_block_version jpeg_v2_0_ip_block;
6268

‎drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -662,6 +662,7 @@ static const struct amdgpu_ring_funcs jpeg_v2_5_dec_ring_vm_funcs = {
662662
.get_rptr = jpeg_v2_5_dec_ring_get_rptr,
663663
.get_wptr = jpeg_v2_5_dec_ring_get_wptr,
664664
.set_wptr = jpeg_v2_5_dec_ring_set_wptr,
665+
.parse_cs = jpeg_v2_dec_ring_parse_cs,
665666
.emit_frame_size =
666667
SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
667668
SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +
@@ -691,6 +692,7 @@ static const struct amdgpu_ring_funcs jpeg_v2_6_dec_ring_vm_funcs = {
691692
.get_rptr = jpeg_v2_5_dec_ring_get_rptr,
692693
.get_wptr = jpeg_v2_5_dec_ring_get_wptr,
693694
.set_wptr = jpeg_v2_5_dec_ring_set_wptr,
695+
.parse_cs = jpeg_v2_dec_ring_parse_cs,
694696
.emit_frame_size =
695697
SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
696698
SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +

‎drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -560,6 +560,7 @@ static const struct amdgpu_ring_funcs jpeg_v3_0_dec_ring_vm_funcs = {
560560
.get_rptr = jpeg_v3_0_dec_ring_get_rptr,
561561
.get_wptr = jpeg_v3_0_dec_ring_get_wptr,
562562
.set_wptr = jpeg_v3_0_dec_ring_set_wptr,
563+
.parse_cs = jpeg_v2_dec_ring_parse_cs,
563564
.emit_frame_size =
564565
SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
565566
SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +

‎drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -727,6 +727,7 @@ static const struct amdgpu_ring_funcs jpeg_v4_0_dec_ring_vm_funcs = {
727727
.get_rptr = jpeg_v4_0_dec_ring_get_rptr,
728728
.get_wptr = jpeg_v4_0_dec_ring_get_wptr,
729729
.set_wptr = jpeg_v4_0_dec_ring_set_wptr,
730+
.parse_cs = jpeg_v2_dec_ring_parse_cs,
730731
.emit_frame_size =
731732
SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
732733
SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +

‎drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.h

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -32,5 +32,4 @@ enum amdgpu_jpeg_v4_0_sub_block {
3232
};
3333

3434
extern const struct amdgpu_ip_block_version jpeg_v4_0_ip_block;
35-
3635
#endif /* __JPEG_V4_0_H__ */

‎drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c

Lines changed: 2 additions & 55 deletions
Original file line numberDiff line numberDiff line change
@@ -23,9 +23,9 @@
2323

2424
#include "amdgpu.h"
2525
#include "amdgpu_jpeg.h"
26-
#include "amdgpu_cs.h"
2726
#include "soc15.h"
2827
#include "soc15d.h"
28+
#include "jpeg_v2_0.h"
2929
#include "jpeg_v4_0_3.h"
3030
#include "mmsch_v4_0_3.h"
3131

@@ -1089,7 +1089,7 @@ static const struct amdgpu_ring_funcs jpeg_v4_0_3_dec_ring_vm_funcs = {
10891089
.get_rptr = jpeg_v4_0_3_dec_ring_get_rptr,
10901090
.get_wptr = jpeg_v4_0_3_dec_ring_get_wptr,
10911091
.set_wptr = jpeg_v4_0_3_dec_ring_set_wptr,
1092-
.parse_cs = jpeg_v4_0_3_dec_ring_parse_cs,
1092+
.parse_cs = jpeg_v2_dec_ring_parse_cs,
10931093
.emit_frame_size =
10941094
SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
10951095
SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +
@@ -1254,56 +1254,3 @@ static void jpeg_v4_0_3_set_ras_funcs(struct amdgpu_device *adev)
12541254
{
12551255
adev->jpeg.ras = &jpeg_v4_0_3_ras;
12561256
}
1257-
1258-
/**
1259-
* jpeg_v4_0_3_dec_ring_parse_cs - command submission parser
1260-
*
1261-
* @parser: Command submission parser context
1262-
* @job: the job to parse
1263-
* @ib: the IB to parse
1264-
*
1265-
* Parse the command stream, return -EINVAL for invalid packet,
1266-
* 0 otherwise
1267-
*/
1268-
int jpeg_v4_0_3_dec_ring_parse_cs(struct amdgpu_cs_parser *parser,
1269-
struct amdgpu_job *job,
1270-
struct amdgpu_ib *ib)
1271-
{
1272-
uint32_t i, reg, res, cond, type;
1273-
struct amdgpu_device *adev = parser->adev;
1274-
1275-
for (i = 0; i < ib->length_dw ; i += 2) {
1276-
reg = CP_PACKETJ_GET_REG(ib->ptr[i]);
1277-
res = CP_PACKETJ_GET_RES(ib->ptr[i]);
1278-
cond = CP_PACKETJ_GET_COND(ib->ptr[i]);
1279-
type = CP_PACKETJ_GET_TYPE(ib->ptr[i]);
1280-
1281-
if (res) /* only support 0 at the moment */
1282-
return -EINVAL;
1283-
1284-
switch (type) {
1285-
case PACKETJ_TYPE0:
1286-
if (cond != PACKETJ_CONDITION_CHECK0 || reg < JPEG_REG_RANGE_START || reg > JPEG_REG_RANGE_END) {
1287-
dev_err(adev->dev, "Invalid packet [0x%08x]!\n", ib->ptr[i]);
1288-
return -EINVAL;
1289-
}
1290-
break;
1291-
case PACKETJ_TYPE3:
1292-
if (cond != PACKETJ_CONDITION_CHECK3 || reg < JPEG_REG_RANGE_START || reg > JPEG_REG_RANGE_END) {
1293-
dev_err(adev->dev, "Invalid packet [0x%08x]!\n", ib->ptr[i]);
1294-
return -EINVAL;
1295-
}
1296-
break;
1297-
case PACKETJ_TYPE6:
1298-
if (ib->ptr[i] == CP_PACKETJ_NOP)
1299-
continue;
1300-
dev_err(adev->dev, "Invalid packet [0x%08x]!\n", ib->ptr[i]);
1301-
return -EINVAL;
1302-
default:
1303-
dev_err(adev->dev, "Unknown packet type %d !\n", type);
1304-
return -EINVAL;
1305-
}
1306-
}
1307-
1308-
return 0;
1309-
}

‎drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.h

Lines changed: 1 addition & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -46,9 +46,6 @@
4646

4747
#define JRBC_DEC_EXTERNAL_REG_WRITE_ADDR 0x18000
4848

49-
#define JPEG_REG_RANGE_START 0x4000
50-
#define JPEG_REG_RANGE_END 0x41c2
51-
5249
extern const struct amdgpu_ip_block_version jpeg_v4_0_3_ip_block;
5350

5451
void jpeg_v4_0_3_dec_ring_emit_ib(struct amdgpu_ring *ring,
@@ -65,7 +62,5 @@ void jpeg_v4_0_3_dec_ring_insert_end(struct amdgpu_ring *ring);
6562
void jpeg_v4_0_3_dec_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val);
6663
void jpeg_v4_0_3_dec_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
6764
uint32_t val, uint32_t mask);
68-
int jpeg_v4_0_3_dec_ring_parse_cs(struct amdgpu_cs_parser *parser,
69-
struct amdgpu_job *job,
70-
struct amdgpu_ib *ib);
65+
7166
#endif /* __JPEG_V4_0_3_H__ */

‎drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -768,6 +768,7 @@ static const struct amdgpu_ring_funcs jpeg_v4_0_5_dec_ring_vm_funcs = {
768768
.get_rptr = jpeg_v4_0_5_dec_ring_get_rptr,
769769
.get_wptr = jpeg_v4_0_5_dec_ring_get_wptr,
770770
.set_wptr = jpeg_v4_0_5_dec_ring_set_wptr,
771+
.parse_cs = jpeg_v2_dec_ring_parse_cs,
771772
.emit_frame_size =
772773
SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
773774
SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +

‎drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -26,6 +26,7 @@
2626
#include "amdgpu_pm.h"
2727
#include "soc15.h"
2828
#include "soc15d.h"
29+
#include "jpeg_v2_0.h"
2930
#include "jpeg_v4_0_3.h"
3031

3132
#include "vcn/vcn_5_0_0_offset.h"
@@ -646,7 +647,7 @@ static const struct amdgpu_ring_funcs jpeg_v5_0_0_dec_ring_vm_funcs = {
646647
.get_rptr = jpeg_v5_0_0_dec_ring_get_rptr,
647648
.get_wptr = jpeg_v5_0_0_dec_ring_get_wptr,
648649
.set_wptr = jpeg_v5_0_0_dec_ring_set_wptr,
649-
.parse_cs = jpeg_v4_0_3_dec_ring_parse_cs,
650+
.parse_cs = jpeg_v2_dec_ring_parse_cs,
650651
.emit_frame_size =
651652
SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
652653
SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +

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