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Merge tag 'samsung-clk-6.13' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into clk-samsung
Pull Samsung SoC clk driver updates from Krzysztof Kozlowski: - Tesla FSD: Move number of clocks from DT binding headers to driver, because these are not an ABI and might change while finishing support for the hardware. - ExynosAutov920: Add clock controller drivers for PERIC1, MISC, HSI0 and HSI1. Context of patch depends on a fix from fixes branch, thus pull in my earlier pull request with fixes. - Google GS101: Do not disable UFS host controller clocks, ever, because gating them does not work well with UFS sleep/power savings. Downstream does not gate them via OS, but uses hardware feature - Automatic Clock Gating - which is not yet supported in upstream. - Exynos8895: New SoC with initial support for clock controllers: FSYS0/1, PERIC0/1, PERIS and TOP. * tag 'samsung-clk-6.13' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux: clk: samsung: Introduce Exynos8895 clock driver clk: samsung: clk-pll: Add support for pll_{1051x,1052x} dt-bindings: clock: samsung: Add Exynos8895 SoC clk: samsung: gs101: make all ufs related clocks critical clk: samsung: exynosautov920: add peric1, misc and hsi0/1 clock support dt-bindings: clock: exynosautov920: add peric1, misc and hsi0/1 clock definitions clk: samsung: Fix out-of-bound access of of_match_node() dt-bindings: clock: samsung: remove define with number of clocks for FSD clk: samsung: fsd: do not define number of clocks in bindings clk: samsung: Fix errors reported by checkpatch clk: samsung: Fix block comment style warnings reported by checkpatch
2 parents 9852d85 + 9174fac commit 31062ea

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-34
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‎Documentation/devicetree/bindings/clock/samsung,exynos8895-clock.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/samsung,exynos8895-clock.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Samsung Exynos8895 SoC clock controller
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maintainers:
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- Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com>
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- Chanwoo Choi <cw00.choi@samsung.com>
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- Krzysztof Kozlowski <krzk@kernel.org>
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description: |
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Exynos8895 clock controller is comprised of several CMU units, generating
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clocks for different domains. Those CMU units are modeled as separate device
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tree nodes, and might depend on each other. The root clock in that root tree
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is an external clock: OSCCLK (26 MHz). This external clock must be defined
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as a fixed-rate clock in dts.
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CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and
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dividers; all other clocks of function blocks (other CMUs) are usually
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derived from CMU_TOP.
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Each clock is assigned an identifier and client nodes can use this identifier
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to specify the clock which they consume. All clocks available for usage
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in clock consumer nodes are defined as preprocessor macros in
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'include/dt-bindings/clock/samsung,exynos8895.h' header.
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properties:
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compatible:
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enum:
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- samsung,exynos8895-cmu-fsys0
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- samsung,exynos8895-cmu-fsys1
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- samsung,exynos8895-cmu-peric0
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- samsung,exynos8895-cmu-peric1
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- samsung,exynos8895-cmu-peris
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- samsung,exynos8895-cmu-top
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clocks:
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minItems: 1
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maxItems: 16
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clock-names:
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minItems: 1
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maxItems: 16
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"#clock-cells":
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const: 1
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reg:
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maxItems: 1
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required:
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- compatible
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- clocks
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- clock-names
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- reg
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- "#clock-cells"
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allOf:
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- if:
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properties:
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compatible:
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contains:
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const: samsung,exynos8895-cmu-fsys0
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then:
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properties:
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clocks:
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items:
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- description: External reference clock (26 MHz)
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- description: CMU_FSYS0 BUS clock (from CMU_TOP)
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- description: CMU_FSYS0 DPGTC clock (from CMU_TOP)
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- description: CMU_FSYS0 MMC_EMBD clock (from CMU_TOP)
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- description: CMU_FSYS0 UFS_EMBD clock (from CMU_TOP)
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- description: CMU_FSYS0 USBDRD30 clock (from CMU_TOP)
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clock-names:
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items:
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- const: oscclk
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- const: bus
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- const: dpgtc
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- const: mmc
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- const: ufs
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- const: usbdrd30
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- if:
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properties:
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compatible:
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contains:
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const: samsung,exynos8895-cmu-fsys1
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then:
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properties:
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clocks:
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items:
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- description: External reference clock (26 MHz)
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- description: CMU_FSYS1 BUS clock (from CMU_TOP)
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- description: CMU_FSYS1 PCIE clock (from CMU_TOP)
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- description: CMU_FSYS1 UFS_CARD clock (from CMU_TOP)
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- description: CMU_FSYS1 MMC_CARD clock (from CMU_TOP)
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clock-names:
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items:
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- const: oscclk
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- const: bus
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- const: pcie
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- const: ufs
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- const: mmc
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- if:
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properties:
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compatible:
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contains:
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const: samsung,exynos8895-cmu-peric0
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then:
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properties:
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clocks:
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items:
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- description: External reference clock (26 MHz)
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- description: CMU_PERIC0 BUS clock (from CMU_TOP)
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- description: CMU_PERIC0 UART_DBG clock (from CMU_TOP)
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- description: CMU_PERIC0 USI00 clock (from CMU_TOP)
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- description: CMU_PERIC0 USI01 clock (from CMU_TOP)
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- description: CMU_PERIC0 USI02 clock (from CMU_TOP)
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- description: CMU_PERIC0 USI03 clock (from CMU_TOP)
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clock-names:
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items:
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- const: oscclk
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- const: bus
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- const: uart
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- const: usi0
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- const: usi1
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- const: usi2
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- const: usi3
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- if:
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properties:
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compatible:
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contains:
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const: samsung,exynos8895-cmu-peric1
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then:
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properties:
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clocks:
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items:
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- description: External reference clock (26 MHz)
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- description: CMU_PERIC1 BUS clock (from CMU_TOP)
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- description: CMU_PERIC1 SPEEDY2 clock (from CMU_TOP)
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- description: CMU_PERIC1 SPI_CAM0 clock (from CMU_TOP)
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- description: CMU_PERIC1 SPI_CAM1 clock (from CMU_TOP)
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- description: CMU_PERIC1 UART_BT clock (from CMU_TOP)
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- description: CMU_PERIC1 USI04 clock (from CMU_TOP)
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- description: CMU_PERIC1 USI05 clock (from CMU_TOP)
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- description: CMU_PERIC1 USI06 clock (from CMU_TOP)
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- description: CMU_PERIC1 USI07 clock (from CMU_TOP)
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- description: CMU_PERIC1 USI08 clock (from CMU_TOP)
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- description: CMU_PERIC1 USI09 clock (from CMU_TOP)
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- description: CMU_PERIC1 USI10 clock (from CMU_TOP)
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- description: CMU_PERIC1 USI11 clock (from CMU_TOP)
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- description: CMU_PERIC1 USI12 clock (from CMU_TOP)
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- description: CMU_PERIC1 USI13 clock (from CMU_TOP)
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clock-names:
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items:
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- const: oscclk
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- const: bus
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- const: speedy
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- const: cam0
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- const: cam1
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- const: uart
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- const: usi4
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- const: usi5
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- const: usi6
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- const: usi7
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- const: usi8
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- const: usi9
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- const: usi10
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- const: usi11
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- const: usi12
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- const: usi13
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- if:
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properties:
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compatible:
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contains:
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const: samsung,exynos8895-cmu-peris
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then:
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properties:
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clocks:
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items:
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- description: External reference clock (26 MHz)
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- description: CMU_PERIS BUS clock (from CMU_TOP)
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clock-names:
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items:
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- const: oscclk
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- const: bus
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- if:
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properties:
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compatible:
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contains:
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const: samsung,exynos8895-cmu-top
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then:
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properties:
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clocks:
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items:
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- description: External reference clock (26 MHz)
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clock-names:
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items:
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- const: oscclk
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/samsung,exynos8895.h>
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cmu_fsys1: clock-controller@11400000 {
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compatible = "samsung,exynos8895-cmu-fsys1";
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reg = <0x11400000 0x8000>;
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#clock-cells = <1>;
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clocks = <&oscclk>,
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<&cmu_top CLK_DOUT_CMU_FSYS1_BUS>,
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<&cmu_top CLK_DOUT_CMU_FSYS1_PCIE>,
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<&cmu_top CLK_DOUT_CMU_FSYS1_UFS_CARD>,
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<&cmu_top CLK_DOUT_CMU_FSYS1_MMC_CARD>;
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clock-names = "oscclk", "bus", "pcie", "ufs", "mmc";
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};
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...

‎drivers/clk/samsung/Makefile

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@@ -20,6 +20,7 @@ obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos-arm64.o
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obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos7.o
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obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos7885.o
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obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos850.o
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obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos8895.o
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obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynosautov9.o
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obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynosautov920.o
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obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-gs101.o

‎drivers/clk/samsung/clk-exynos-audss.c

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* Author: Padmavathi Venna <padma.v@samsung.com>
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*
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* Common Clock Framework support for Audio Subsystem Clock Controller.
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*/
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*/
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#include <linux/slab.h>
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#include <linux/io.h>

‎drivers/clk/samsung/clk-exynos3250.c

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@@ -260,7 +260,7 @@ static const struct samsung_mux_clock mux_clks[] __initconst = {
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/* SRC_TOP0 */
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MUX(CLK_MOUT_EBI, "mout_ebi", mout_ebi_p, SRC_TOP0, 28, 1),
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MUX(CLK_MOUT_ACLK_200, "mout_aclk_200", group_div_mpll_pre_p,SRC_TOP0, 24, 1),
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MUX(CLK_MOUT_ACLK_200, "mout_aclk_200", group_div_mpll_pre_p, SRC_TOP0, 24, 1),
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MUX(CLK_MOUT_ACLK_160, "mout_aclk_160", group_div_mpll_pre_p, SRC_TOP0, 20, 1),
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MUX(CLK_MOUT_ACLK_100, "mout_aclk_100", group_div_mpll_pre_p, SRC_TOP0, 16, 1),
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MUX(CLK_MOUT_ACLK_266_1, "mout_aclk_266_1", mout_aclk_266_1_p, SRC_TOP0, 14, 1),

‎drivers/clk/samsung/clk-exynos4.c

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* Author: Thomas Abraham <thomas.ab@samsung.com>
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*
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* Common Clock Framework support for all Exynos4 SoCs.
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*/
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*/
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#include <dt-bindings/clock/exynos4.h>
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#include <linux/slab.h>

‎drivers/clk/samsung/clk-exynos4412-isp.c

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* Author: Marek Szyprowski <m.szyprowski@samsung.com>
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*
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* Common Clock Framework support for Exynos4412 ISP module.
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*/
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*/
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#include <dt-bindings/clock/exynos4.h>
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#include <linux/slab.h>

‎drivers/clk/samsung/clk-exynos5250.c

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* Author: Thomas Abraham <thomas.ab@samsung.com>
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*
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* Common Clock Framework support for Exynos5250 SoC.
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*/
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*/
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#include <dt-bindings/clock/exynos5250.h>
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#include <linux/clk-provider.h>

‎drivers/clk/samsung/clk-exynos5260.c

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@@ -1458,7 +1458,7 @@ static const struct samsung_fixed_rate_clock fixed_rate_clks[] __initconst = {
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FRATE(PHYCLK_HDMI_LINK_O_TMDS_CLKHI, "phyclk_hdmi_link_o_tmds_clkhi",
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NULL, 0, 125000000),
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FRATE(PHYCLK_MIPI_DPHY_4L_M_TXBYTECLKHS,
1461-
"phyclk_mipi_dphy_4l_m_txbyte_clkhs" , NULL,
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"phyclk_mipi_dphy_4l_m_txbyte_clkhs", NULL,
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0, 187500000),
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FRATE(PHYCLK_DPTX_PHY_O_REF_CLK_24M, "phyclk_dptx_phy_o_ref_clk_24m",
14641464
NULL, 0, 24000000),
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16291629
mout_isp1_media_400_p,
16301630
MUX_SEL_TOP_ISP10, 4, 1),
16311631
MUX(TOP_MOUT_ACLK_ISP1_400, "mout_aclk_isp1_400", mout_aclk_isp1_400_p,
1632-
MUX_SEL_TOP_ISP10, 8 , 1),
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MUX_SEL_TOP_ISP10, 8, 1),
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MUX(TOP_MOUT_ISP1_MEDIA_266, "mout_isp1_media_266",
16341634
mout_isp1_media_266_p,
16351635
MUX_SEL_TOP_ISP10, 16, 1),

‎drivers/clk/samsung/clk-exynos5410.c

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* Author: Tarek Dakhran <t.dakhran@samsung.com>
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*
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* Common Clock Framework support for Exynos5410 SoC.
7-
*/
7+
*/
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#include <dt-bindings/clock/exynos5410.h>
1010

‎drivers/clk/samsung/clk-exynos5420.c

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@@ -5,7 +5,7 @@
55
* Chander Kashyap <k.chander@samsung.com>
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*
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* Common Clock Framework support for Exynos5420 SoC.
8-
*/
8+
*/
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1010
#include <dt-bindings/clock/exynos5420.h>
1111
#include <linux/slab.h>
@@ -295,8 +295,8 @@ static const struct samsung_clk_reg_dump exynos5420_set_clksrc[] = {
295295
/* list of all parent clocks */
296296
PNAME(mout_mspll_cpu_p) = {"mout_sclk_cpll", "mout_sclk_dpll",
297297
"mout_sclk_mpll", "mout_sclk_spll"};
298-
PNAME(mout_cpu_p) = {"mout_apll" , "mout_mspll_cpu"};
299-
PNAME(mout_kfc_p) = {"mout_kpll" , "mout_mspll_kfc"};
298+
PNAME(mout_cpu_p) = {"mout_apll", "mout_mspll_cpu"};
299+
PNAME(mout_kfc_p) = {"mout_kpll", "mout_mspll_kfc"};
300300
PNAME(mout_apll_p) = {"fin_pll", "fout_apll"};
301301
PNAME(mout_bpll_p) = {"fin_pll", "fout_bpll"};
302302
PNAME(mout_cpll_p) = {"fin_pll", "fout_cpll"};

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