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airliedairlied
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Merge tag 'drm-intel-next-2023-08-10' of git://anongit.freedesktop.org/drm/drm-intel into drm-next
- Display SDVO fixes (Juha-Pekka, Jani) - Taking Stolen handling out of FBC code (Jouni) - Replace acronym with full platform name in defines (Dnyaneshwar, A\ nusha) - Display IRQ cleanups (Jani) - Initialize display version numbers (Luca) Signed-off-by: Dave Airlie <airlied@redhat.com> From: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/ZNVAR53jmvA1p6D5@intel.com
2 parents e6b17f5 + 129ebb5 commit 2b9d7b6

38 files changed

+339
-255
lines changed

‎drivers/gpu/drm/i915/display/icl_dsi.c

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -444,7 +444,8 @@ static void gen11_dsi_config_phy_lanes_sequence(struct intel_encoder *encoder)
444444
intel_de_write(dev_priv, ICL_PORT_TX_DW2_GRP(phy), tmp);
445445

446446
/* For EHL, TGL, set latency optimization for PCS_DW1 lanes */
447-
if (IS_JSL_EHL(dev_priv) || (DISPLAY_VER(dev_priv) >= 12)) {
447+
if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv) ||
448+
(DISPLAY_VER(dev_priv) >= 12)) {
448449
intel_de_rmw(dev_priv, ICL_PORT_PCS_DW1_AUX(phy),
449450
LATENCY_OPTIM_MASK, LATENCY_OPTIM_VAL(0));
450451

@@ -553,7 +554,7 @@ gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder,
553554
}
554555
}
555556

556-
if (IS_JSL_EHL(dev_priv)) {
557+
if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) {
557558
for_each_dsi_phy(phy, intel_dsi->phys)
558559
intel_de_rmw(dev_priv, ICL_DPHY_CHKN(phy),
559560
0, ICL_DPHY_CHKN_AFE_OVER_PPI_STRAP);

‎drivers/gpu/drm/i915/display/intel_cdclk.c

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -470,7 +470,7 @@ static void hsw_get_cdclk(struct drm_i915_private *dev_priv,
470470
cdclk_config->cdclk = 450000;
471471
else if (freq == LCPLL_CLK_FREQ_450)
472472
cdclk_config->cdclk = 450000;
473-
else if (IS_HSW_ULT(dev_priv))
473+
else if (IS_HASWELL_ULT(dev_priv))
474474
cdclk_config->cdclk = 337500;
475475
else
476476
cdclk_config->cdclk = 540000;
@@ -3155,7 +3155,7 @@ static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
31553155
*/
31563156
void intel_update_max_cdclk(struct drm_i915_private *dev_priv)
31573157
{
3158-
if (IS_JSL_EHL(dev_priv)) {
3158+
if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) {
31593159
if (dev_priv->display.cdclk.hw.ref == 24000)
31603160
dev_priv->display.cdclk.max_cdclk_freq = 552000;
31613161
else
@@ -3200,9 +3200,9 @@ void intel_update_max_cdclk(struct drm_i915_private *dev_priv)
32003200
*/
32013201
if (intel_de_read(dev_priv, FUSE_STRAP) & HSW_CDCLK_LIMIT)
32023202
dev_priv->display.cdclk.max_cdclk_freq = 450000;
3203-
else if (IS_BDW_ULX(dev_priv))
3203+
else if (IS_BROADWELL_ULX(dev_priv))
32043204
dev_priv->display.cdclk.max_cdclk_freq = 450000;
3205-
else if (IS_BDW_ULT(dev_priv))
3205+
else if (IS_BROADWELL_ULT(dev_priv))
32063206
dev_priv->display.cdclk.max_cdclk_freq = 540000;
32073207
else
32083208
dev_priv->display.cdclk.max_cdclk_freq = 675000;
@@ -3567,10 +3567,10 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
35673567
dev_priv->display.cdclk.table = dg2_cdclk_table;
35683568
} else if (IS_ALDERLAKE_P(dev_priv)) {
35693569
/* Wa_22011320316:adl-p[a0] */
3570-
if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) {
3570+
if (IS_ALDERLAKE_P(dev_priv) && IS_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) {
35713571
dev_priv->display.cdclk.table = adlp_a_step_cdclk_table;
35723572
dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs;
3573-
} else if (IS_ADLP_RPLU(dev_priv)) {
3573+
} else if (IS_RAPTORLAKE_U(dev_priv)) {
35743574
dev_priv->display.cdclk.table = rplu_cdclk_table;
35753575
dev_priv->display.funcs.cdclk = &rplu_cdclk_funcs;
35763576
} else {
@@ -3583,7 +3583,7 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
35833583
} else if (DISPLAY_VER(dev_priv) >= 12) {
35843584
dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs;
35853585
dev_priv->display.cdclk.table = icl_cdclk_table;
3586-
} else if (IS_JSL_EHL(dev_priv)) {
3586+
} else if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) {
35873587
dev_priv->display.funcs.cdclk = &ehl_cdclk_funcs;
35883588
dev_priv->display.cdclk.table = icl_cdclk_table;
35893589
} else if (DISPLAY_VER(dev_priv) >= 11) {

‎drivers/gpu/drm/i915/display/intel_combo_phy.c

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -141,7 +141,7 @@ static bool has_phy_misc(struct drm_i915_private *i915, enum phy phy)
141141

142142
if (IS_ALDERLAKE_S(i915))
143143
return phy == PHY_A;
144-
else if (IS_JSL_EHL(i915) ||
144+
else if ((IS_JASPERLAKE(i915) || IS_ELKHARTLAKE(i915)) ||
145145
IS_ROCKETLAKE(i915) ||
146146
IS_DG1(i915))
147147
return phy < PHY_C;
@@ -242,7 +242,7 @@ static bool icl_combo_phy_verify_state(struct drm_i915_private *dev_priv,
242242
ret &= check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW8(phy),
243243
IREFGEN, IREFGEN);
244244

245-
if (IS_JSL_EHL(dev_priv)) {
245+
if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) {
246246
if (ehl_vbt_ddi_d_present(dev_priv))
247247
expected_val = ICL_PHY_MISC_MUX_DDID;
248248

@@ -333,7 +333,8 @@ static void icl_combo_phys_init(struct drm_i915_private *dev_priv)
333333
* "internal" child devices.
334334
*/
335335
val = intel_de_read(dev_priv, ICL_PHY_MISC(phy));
336-
if (IS_JSL_EHL(dev_priv) && phy == PHY_A) {
336+
if ((IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) &&
337+
phy == PHY_A) {
337338
val &= ~ICL_PHY_MISC_MUX_DDID;
338339

339340
if (ehl_vbt_ddi_d_present(dev_priv))

‎drivers/gpu/drm/i915/display/intel_ddi.c

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -3583,7 +3583,8 @@ void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv,
35833583
{
35843584
if (DISPLAY_VER(dev_priv) >= 12 && crtc_state->port_clock > 594000)
35853585
crtc_state->min_voltage_level = 2;
3586-
else if (IS_JSL_EHL(dev_priv) && crtc_state->port_clock > 594000)
3586+
else if ((IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) &&
3587+
crtc_state->port_clock > 594000)
35873588
crtc_state->min_voltage_level = 3;
35883589
else if (DISPLAY_VER(dev_priv) >= 11 && crtc_state->port_clock > 594000)
35893590
crtc_state->min_voltage_level = 1;
@@ -4878,7 +4879,7 @@ void intel_ddi_init(struct drm_i915_private *dev_priv,
48784879
encoder->disable_clock = dg1_ddi_disable_clock;
48794880
encoder->is_clock_enabled = dg1_ddi_is_clock_enabled;
48804881
encoder->get_config = dg1_ddi_get_config;
4881-
} else if (IS_JSL_EHL(dev_priv)) {
4882+
} else if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) {
48824883
if (intel_ddi_is_tc(dev_priv, port)) {
48834884
encoder->enable_clock = jsl_ddi_tc_enable_clock;
48844885
encoder->disable_clock = jsl_ddi_tc_disable_clock;
@@ -4949,7 +4950,7 @@ void intel_ddi_init(struct drm_i915_private *dev_priv,
49494950
encoder->hpd_pin = rkl_hpd_pin(dev_priv, port);
49504951
else if (DISPLAY_VER(dev_priv) >= 12)
49514952
encoder->hpd_pin = tgl_hpd_pin(dev_priv, port);
4952-
else if (IS_JSL_EHL(dev_priv))
4953+
else if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv))
49534954
encoder->hpd_pin = ehl_hpd_pin(dev_priv, port);
49544955
else if (DISPLAY_VER(dev_priv) == 11)
49554956
encoder->hpd_pin = icl_hpd_pin(dev_priv, port);

‎drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1410,7 +1410,7 @@ tgl_get_combo_buf_trans_dp(struct intel_encoder *encoder,
14101410
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
14111411

14121412
if (crtc_state->port_clock > 270000) {
1413-
if (IS_TGL_UY(dev_priv)) {
1413+
if (IS_TIGERLAKE_UY(dev_priv)) {
14141414
return intel_get_buf_trans(&tgl_uy_combo_phy_trans_dp_hbr2,
14151415
n_entries);
14161416
} else {
@@ -1740,15 +1740,15 @@ void intel_ddi_buf_trans_init(struct intel_encoder *encoder)
17401740
encoder->get_buf_trans = icl_get_mg_buf_trans;
17411741
} else if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) {
17421742
encoder->get_buf_trans = bxt_get_buf_trans;
1743-
} else if (IS_CML_ULX(i915) || IS_CFL_ULX(i915) || IS_KBL_ULX(i915)) {
1743+
} else if (IS_COMETLAKE_ULX(i915) || IS_COFFEELAKE_ULX(i915) || IS_KABYLAKE_ULX(i915)) {
17441744
encoder->get_buf_trans = kbl_y_get_buf_trans;
1745-
} else if (IS_CML_ULT(i915) || IS_CFL_ULT(i915) || IS_KBL_ULT(i915)) {
1745+
} else if (IS_COMETLAKE_ULT(i915) || IS_COFFEELAKE_ULT(i915) || IS_KABYLAKE_ULT(i915)) {
17461746
encoder->get_buf_trans = kbl_u_get_buf_trans;
17471747
} else if (IS_COMETLAKE(i915) || IS_COFFEELAKE(i915) || IS_KABYLAKE(i915)) {
17481748
encoder->get_buf_trans = kbl_get_buf_trans;
1749-
} else if (IS_SKL_ULX(i915)) {
1749+
} else if (IS_SKYLAKE_ULX(i915)) {
17501750
encoder->get_buf_trans = skl_y_get_buf_trans;
1751-
} else if (IS_SKL_ULT(i915)) {
1751+
} else if (IS_SKYLAKE_ULT(i915)) {
17521752
encoder->get_buf_trans = skl_u_get_buf_trans;
17531753
} else if (IS_SKYLAKE(i915)) {
17541754
encoder->get_buf_trans = skl_get_buf_trans;

‎drivers/gpu/drm/i915/display/intel_display.c

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1749,7 +1749,7 @@ bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy)
17491749
return phy <= PHY_E;
17501750
else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
17511751
return phy <= PHY_D;
1752-
else if (IS_JSL_EHL(dev_priv))
1752+
else if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv))
17531753
return phy <= PHY_C;
17541754
else if (IS_ALDERLAKE_P(dev_priv) || IS_DISPLAY_VER(dev_priv, 11, 12))
17551755
return phy <= PHY_B;
@@ -1801,7 +1801,8 @@ enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port)
18011801
return PHY_B + port - PORT_TC1;
18021802
else if ((IS_DG1(i915) || IS_ROCKETLAKE(i915)) && port >= PORT_TC1)
18031803
return PHY_C + port - PORT_TC1;
1804-
else if (IS_JSL_EHL(i915) && port == PORT_D)
1804+
else if ((IS_JASPERLAKE(i915) || IS_ELKHARTLAKE(i915)) &&
1805+
port == PORT_D)
18051806
return PHY_A;
18061807

18071808
return PHY_A + port - PORT_A;
@@ -7377,7 +7378,7 @@ static bool intel_ddi_crt_present(struct drm_i915_private *dev_priv)
73777378
if (DISPLAY_VER(dev_priv) >= 9)
73787379
return false;
73797380

7380-
if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv))
7381+
if (IS_HASWELL_ULT(dev_priv) || IS_BROADWELL_ULT(dev_priv))
73817382
return false;
73827383

73837384
if (HAS_PCH_LPT_H(dev_priv) &&

‎drivers/gpu/drm/i915/display/intel_display_device.c

Lines changed: 34 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -724,10 +724,24 @@ static const struct intel_display_device_info xe_lpdp_display = {
724724
BIT(PORT_TC1) | BIT(PORT_TC2) | BIT(PORT_TC3) | BIT(PORT_TC4),
725725
};
726726

727+
/*
728+
* Separate detection for no display cases to keep the display id array simple.
729+
*
730+
* IVB Q requires subvendor and subdevice matching to differentiate from IVB D
731+
* GT2 server.
732+
*/
733+
static bool has_no_display(struct pci_dev *pdev)
734+
{
735+
static const struct pci_device_id ids[] = {
736+
INTEL_IVB_Q_IDS(0),
737+
{}
738+
};
739+
740+
return pci_match_id(ids, pdev);
741+
}
742+
727743
#undef INTEL_VGA_DEVICE
728-
#undef INTEL_QUANTA_VGA_DEVICE
729744
#define INTEL_VGA_DEVICE(id, info) { id, info }
730-
#define INTEL_QUANTA_VGA_DEVICE(info) { 0x16a, info }
731745

732746
static const struct {
733747
u32 devid;
@@ -752,7 +766,6 @@ static const struct {
752766
INTEL_IRONLAKE_M_IDS(&ilk_m_display),
753767
INTEL_SNB_D_IDS(&snb_display),
754768
INTEL_SNB_M_IDS(&snb_display),
755-
INTEL_IVB_Q_IDS(NULL), /* must be first IVB in list */
756769
INTEL_IVB_M_IDS(&ivb_display),
757770
INTEL_IVB_D_IDS(&ivb_display),
758771
INTEL_HSW_IDS(&hsw_display),
@@ -800,6 +813,15 @@ probe_gmdid_display(struct drm_i915_private *i915, u16 *ver, u16 *rel, u16 *step
800813
u32 val;
801814
int i;
802815

816+
/* The caller expects to ver, rel and step to be initialized
817+
* here, and there's no good way to check when there was a
818+
* failure and no_display was returned. So initialize all these
819+
* values here zero, to be sure.
820+
*/
821+
*ver = 0;
822+
*rel = 0;
823+
*step = 0;
824+
803825
addr = pci_iomap_range(pdev, 0, i915_mmio_reg_offset(GMD_ID_DISPLAY), sizeof(u32));
804826
if (!addr) {
805827
drm_err(&i915->drm, "Cannot map MMIO BAR to read display GMD_ID\n");
@@ -809,9 +831,10 @@ probe_gmdid_display(struct drm_i915_private *i915, u16 *ver, u16 *rel, u16 *step
809831
val = ioread32(addr);
810832
pci_iounmap(pdev, addr);
811833

812-
if (val == 0)
813-
/* Platform doesn't have display */
834+
if (val == 0) {
835+
drm_dbg_kms(&i915->drm, "Device doesn't have display\n");
814836
return &no_display;
837+
}
815838

816839
*ver = REG_FIELD_GET(GMD_ID_ARCH_MASK, val);
817840
*rel = REG_FIELD_GET(GMD_ID_RELEASE_MASK, val);
@@ -837,6 +860,11 @@ intel_display_device_probe(struct drm_i915_private *i915, bool has_gmdid,
837860
if (has_gmdid)
838861
return probe_gmdid_display(i915, gmdid_ver, gmdid_rel, gmdid_step);
839862

863+
if (has_no_display(pdev)) {
864+
drm_dbg_kms(&i915->drm, "Device doesn't have display\n");
865+
return &no_display;
866+
}
867+
840868
for (i = 0; i < ARRAY_SIZE(intel_display_ids); i++) {
841869
if (intel_display_ids[i].devid == pdev->device)
842870
return intel_display_ids[i].info;
@@ -858,7 +886,7 @@ void intel_display_device_info_runtime_init(struct drm_i915_private *i915)
858886
BUILD_BUG_ON(BITS_PER_TYPE(display_runtime->port_mask) < I915_MAX_PORTS);
859887

860888
/* Wa_14011765242: adl-s A0,A1 */
861-
if (IS_ADLS_DISPLAY_STEP(i915, STEP_A0, STEP_A2))
889+
if (IS_ALDERLAKE_S(i915) && IS_DISPLAY_STEP(i915, STEP_A0, STEP_A2))
862890
for_each_pipe(i915, pipe)
863891
display_runtime->num_scalers[pipe] = 0;
864892
else if (DISPLAY_VER(i915) >= 11) {

‎drivers/gpu/drm/i915/display/intel_display_device.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -54,7 +54,7 @@ struct drm_printer;
5454
#define HAS_GMCH(i915) (DISPLAY_INFO(i915)->has_gmch)
5555
#define HAS_HW_SAGV_WM(i915) (DISPLAY_VER(i915) >= 13 && !IS_DGFX(i915))
5656
#define HAS_IPC(i915) (DISPLAY_INFO(i915)->has_ipc)
57-
#define HAS_IPS(i915) (IS_HSW_ULT(i915) || IS_BROADWELL(i915))
57+
#define HAS_IPS(i915) (IS_HASWELL_ULT(i915) || IS_BROADWELL(i915))
5858
#define HAS_LSPCON(i915) (IS_DISPLAY_VER(i915, 9, 10))
5959
#define HAS_MBUS_JOINING(i915) (IS_ALDERLAKE_P(i915) || DISPLAY_VER(i915) >= 14)
6060
#define HAS_MSO(i915) (DISPLAY_VER(i915) >= 12)

‎drivers/gpu/drm/i915/display/intel_display_driver.c

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -28,6 +28,7 @@
2828
#include "intel_crtc.h"
2929
#include "intel_display_debugfs.h"
3030
#include "intel_display_driver.h"
31+
#include "intel_display_irq.h"
3132
#include "intel_display_power.h"
3233
#include "intel_display_types.h"
3334
#include "intel_dkl_phy.h"
@@ -177,6 +178,7 @@ void intel_display_driver_early_probe(struct drm_i915_private *i915)
177178
if (!HAS_DISPLAY(i915))
178179
return;
179180

181+
intel_display_irq_init(i915);
180182
intel_dkl_phy_init(i915);
181183
intel_color_init_hooks(i915);
182184
intel_init_cdclk_hooks(i915);

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