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Imran Shaikandersson
Imran Shaik
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andersson
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clk: qcom: Add support for Camera Clock Controller on QCS8300
The QCS8300 Camera clock controller is a derivative of SA8775P, but has few additional clocks and offset differences. Hence, add support for QCS8300 Camera clock controller by extending the SA8775P CamCC. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Imran Shaik <quic_imrashai@quicinc.com> Link: https://lore.kernel.org/r/20250327-qcs8300-mm-patches-v6-1-b3fbde2820a6@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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‎drivers/clk/qcom/camcc-sa8775p.c

Lines changed: 98 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -10,7 +10,7 @@
1010
#include <linux/pm_runtime.h>
1111
#include <linux/regmap.h>
1212

13-
#include <dt-bindings/clock/qcom,sa8775p-camcc.h>
13+
#include <dt-bindings/clock/qcom,qcs8300-camcc.h>
1414

1515
#include "clk-alpha-pll.h"
1616
#include "clk-branch.h"
@@ -1681,6 +1681,24 @@ static struct clk_branch cam_cc_sm_obs_clk = {
16811681
},
16821682
};
16831683

1684+
static struct clk_branch cam_cc_titan_top_accu_shift_clk = {
1685+
.halt_reg = 0x131f0,
1686+
.halt_check = BRANCH_HALT_VOTED,
1687+
.clkr = {
1688+
.enable_reg = 0x131f0,
1689+
.enable_mask = BIT(0),
1690+
.hw.init = &(const struct clk_init_data) {
1691+
.name = "cam_cc_titan_top_accu_shift_clk",
1692+
.parent_hws = (const struct clk_hw*[]) {
1693+
&cam_cc_xo_clk_src.clkr.hw,
1694+
},
1695+
.num_parents = 1,
1696+
.flags = CLK_SET_RATE_PARENT,
1697+
.ops = &clk_branch2_ops,
1698+
},
1699+
},
1700+
};
1701+
16841702
static struct gdsc cam_cc_titan_top_gdsc = {
16851703
.gdscr = 0x131bc,
16861704
.en_rest_wait_val = 0x2,
@@ -1775,6 +1793,7 @@ static struct clk_regmap *cam_cc_sa8775p_clocks[] = {
17751793
[CAM_CC_SLEEP_CLK_SRC] = &cam_cc_sleep_clk_src.clkr,
17761794
[CAM_CC_SLOW_AHB_CLK_SRC] = &cam_cc_slow_ahb_clk_src.clkr,
17771795
[CAM_CC_SM_OBS_CLK] = &cam_cc_sm_obs_clk.clkr,
1796+
[CAM_CC_TITAN_TOP_ACCU_SHIFT_CLK] = NULL,
17781797
[CAM_CC_XO_CLK_SRC] = &cam_cc_xo_clk_src.clkr,
17791798
[CAM_CC_QDSS_DEBUG_XO_CLK] = &cam_cc_qdss_debug_xo_clk.clkr,
17801799
};
@@ -1811,6 +1830,7 @@ static const struct qcom_cc_desc cam_cc_sa8775p_desc = {
18111830
};
18121831

18131832
static const struct of_device_id cam_cc_sa8775p_match_table[] = {
1833+
{ .compatible = "qcom,qcs8300-camcc" },
18141834
{ .compatible = "qcom,sa8775p-camcc" },
18151835
{ }
18161836
};
@@ -1841,10 +1861,83 @@ static int cam_cc_sa8775p_probe(struct platform_device *pdev)
18411861
clk_lucid_evo_pll_configure(&cam_cc_pll4, regmap, &cam_cc_pll4_config);
18421862
clk_lucid_evo_pll_configure(&cam_cc_pll5, regmap, &cam_cc_pll5_config);
18431863

1844-
/* Keep some clocks always enabled */
1845-
qcom_branch_set_clk_en(regmap, 0x13194); /* CAM_CC_CAMNOC_XO_CLK */
1846-
qcom_branch_set_clk_en(regmap, 0x131ec); /* CAM_CC_GDSC_CLK */
1847-
qcom_branch_set_clk_en(regmap, 0x13208); /* CAM_CC_SLEEP_CLK */
1864+
if (device_is_compatible(&pdev->dev, "qcom,qcs8300-camcc")) {
1865+
cam_cc_camnoc_axi_clk_src.cmd_rcgr = 0x13154;
1866+
cam_cc_camnoc_axi_clk.halt_reg = 0x1316c;
1867+
cam_cc_camnoc_axi_clk.clkr.enable_reg = 0x1316c;
1868+
cam_cc_camnoc_dcd_xo_clk.halt_reg = 0x13174;
1869+
cam_cc_camnoc_dcd_xo_clk.clkr.enable_reg = 0x13174;
1870+
1871+
cam_cc_csi0phytimer_clk_src.cmd_rcgr = 0x15054;
1872+
cam_cc_csi1phytimer_clk_src.cmd_rcgr = 0x15078;
1873+
cam_cc_csi2phytimer_clk_src.cmd_rcgr = 0x15098;
1874+
cam_cc_csid_clk_src.cmd_rcgr = 0x13134;
1875+
1876+
cam_cc_mclk0_clk_src.cmd_rcgr = 0x15000;
1877+
cam_cc_mclk1_clk_src.cmd_rcgr = 0x1501c;
1878+
cam_cc_mclk2_clk_src.cmd_rcgr = 0x15038;
1879+
1880+
cam_cc_fast_ahb_clk_src.cmd_rcgr = 0x13104;
1881+
cam_cc_slow_ahb_clk_src.cmd_rcgr = 0x1311c;
1882+
cam_cc_xo_clk_src.cmd_rcgr = 0x131b8;
1883+
cam_cc_sleep_clk_src.cmd_rcgr = 0x131d4;
1884+
1885+
cam_cc_core_ahb_clk.halt_reg = 0x131b4;
1886+
cam_cc_core_ahb_clk.clkr.enable_reg = 0x131b4;
1887+
1888+
cam_cc_cpas_ahb_clk.halt_reg = 0x130f4;
1889+
cam_cc_cpas_ahb_clk.clkr.enable_reg = 0x130f4;
1890+
cam_cc_cpas_fast_ahb_clk.halt_reg = 0x130fc;
1891+
cam_cc_cpas_fast_ahb_clk.clkr.enable_reg = 0x130fc;
1892+
1893+
cam_cc_csi0phytimer_clk.halt_reg = 0x1506c;
1894+
cam_cc_csi0phytimer_clk.clkr.enable_reg = 0x1506c;
1895+
cam_cc_csi1phytimer_clk.halt_reg = 0x15090;
1896+
cam_cc_csi1phytimer_clk.clkr.enable_reg = 0x15090;
1897+
cam_cc_csi2phytimer_clk.halt_reg = 0x150b0;
1898+
cam_cc_csi2phytimer_clk.clkr.enable_reg = 0x150b0;
1899+
cam_cc_csid_clk.halt_reg = 0x1314c;
1900+
cam_cc_csid_clk.clkr.enable_reg = 0x1314c;
1901+
cam_cc_csid_csiphy_rx_clk.halt_reg = 0x15074;
1902+
cam_cc_csid_csiphy_rx_clk.clkr.enable_reg = 0x15074;
1903+
cam_cc_csiphy0_clk.halt_reg = 0x15070;
1904+
cam_cc_csiphy0_clk.clkr.enable_reg = 0x15070;
1905+
cam_cc_csiphy1_clk.halt_reg = 0x15094;
1906+
cam_cc_csiphy1_clk.clkr.enable_reg = 0x15094;
1907+
cam_cc_csiphy2_clk.halt_reg = 0x150b4;
1908+
cam_cc_csiphy2_clk.clkr.enable_reg = 0x150b4;
1909+
1910+
cam_cc_mclk0_clk.halt_reg = 0x15018;
1911+
cam_cc_mclk0_clk.clkr.enable_reg = 0x15018;
1912+
cam_cc_mclk1_clk.halt_reg = 0x15034;
1913+
cam_cc_mclk1_clk.clkr.enable_reg = 0x15034;
1914+
cam_cc_mclk2_clk.halt_reg = 0x15050;
1915+
cam_cc_mclk2_clk.clkr.enable_reg = 0x15050;
1916+
cam_cc_qdss_debug_xo_clk.halt_reg = 0x1319c;
1917+
cam_cc_qdss_debug_xo_clk.clkr.enable_reg = 0x1319c;
1918+
1919+
cam_cc_titan_top_gdsc.gdscr = 0x131a0;
1920+
1921+
cam_cc_sa8775p_clocks[CAM_CC_CCI_3_CLK] = NULL;
1922+
cam_cc_sa8775p_clocks[CAM_CC_CCI_3_CLK_SRC] = NULL;
1923+
cam_cc_sa8775p_clocks[CAM_CC_CSI3PHYTIMER_CLK] = NULL;
1924+
cam_cc_sa8775p_clocks[CAM_CC_CSI3PHYTIMER_CLK_SRC] = NULL;
1925+
cam_cc_sa8775p_clocks[CAM_CC_CSIPHY3_CLK] = NULL;
1926+
cam_cc_sa8775p_clocks[CAM_CC_MCLK3_CLK] = NULL;
1927+
cam_cc_sa8775p_clocks[CAM_CC_MCLK3_CLK_SRC] = NULL;
1928+
cam_cc_sa8775p_clocks[CAM_CC_TITAN_TOP_ACCU_SHIFT_CLK] =
1929+
&cam_cc_titan_top_accu_shift_clk.clkr;
1930+
1931+
/* Keep some clocks always enabled */
1932+
qcom_branch_set_clk_en(regmap, 0x13178); /* CAM_CC_CAMNOC_XO_CLK */
1933+
qcom_branch_set_clk_en(regmap, 0x131d0); /* CAM_CC_GDSC_CLK */
1934+
qcom_branch_set_clk_en(regmap, 0x131ec); /* CAM_CC_SLEEP_CLK */
1935+
} else {
1936+
/* Keep some clocks always enabled */
1937+
qcom_branch_set_clk_en(regmap, 0x13194); /* CAM_CC_CAMNOC_XO_CLK */
1938+
qcom_branch_set_clk_en(regmap, 0x131ec); /* CAM_CC_GDSC_CLK */
1939+
qcom_branch_set_clk_en(regmap, 0x13208); /* CAM_CC_SLEEP_CLK */
1940+
}
18481941

18491942
ret = qcom_cc_really_probe(&pdev->dev, &cam_cc_sa8775p_desc, regmap);
18501943

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