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phy: qualcomm: qmp-pcie: add support for SAR2130P
Add PCIe QMP PHY configuration for the Qualcomm SAR2130P platform. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20241021-sar2130p-phys-v2-6-d883acf170f7@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
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‎drivers/phy/qualcomm/phy-qcom-qmp-pcie.c

Lines changed: 141 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2802,6 +2802,101 @@ static const struct qmp_phy_init_tbl sa8775p_qmp_gen4x2_pcie_ep_pcs_alt_tbl[] =
28022802
QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_INSIG_SW_CTRL7, 0x00),
28032803
};
28042804

2805+
static const struct qmp_phy_init_tbl sar2130p_qmp_gen3x2_pcie_rc_serdes_tbl[] = {
2806+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01),
2807+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x31),
2808+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x01),
2809+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0xff),
2810+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x06),
2811+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
2812+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE1, 0x06),
2813+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_ENABLE1, 0x90),
2814+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYS_CLK_CTRL, 0x82),
2815+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x07),
2816+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x02),
2817+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x02),
2818+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16),
2819+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x16),
2820+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36),
2821+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x36),
2822+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x08),
2823+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0e),
2824+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x42),
2825+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x08),
2826+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x1a),
2827+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x14),
2828+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x34),
2829+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x82),
2830+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x68),
2831+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0xab),
2832+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xea),
2833+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x02),
2834+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE1, 0xab),
2835+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE1, 0xaa),
2836+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE1, 0x02),
2837+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x14),
2838+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_SELECT, 0x34),
2839+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x01),
2840+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORECLK_DIV_MODE1, 0x04),
2841+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x16),
2842+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_ADDITIONAL_MISC_3, 0x0f),
2843+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0xa0),
2844+
};
2845+
2846+
static const struct qmp_phy_init_tbl sar2130p_qmp_gen3x2_pcie_pcs_lane1_tbl[] = {
2847+
QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_LANE1_INSIG_SW_CTRL2, 0x01),
2848+
QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_LANE1_INSIG_MX_CTRL2, 0x01),
2849+
};
2850+
2851+
static const struct qmp_phy_init_tbl sar2130p_qmp_gen3x2_pcie_rc_tx_tbl[] = {
2852+
QMP_PHY_INIT_CFG_LANE(QSERDES_V6_TX_BIST_MODE_LANENO, 0x00, 2),
2853+
};
2854+
2855+
static const struct qmp_phy_init_tbl sar2130p_qmp_gen3x2_pcie_rc_pcs_tbl[] = {
2856+
QMP_PHY_INIT_CFG(QPHY_V6_PCS_G12S1_TXDEEMPH_M6DB, 0x17),
2857+
QMP_PHY_INIT_CFG(QPHY_V6_PCS_G3S2_PRE_GAIN, 0x2e),
2858+
};
2859+
2860+
static const struct qmp_phy_init_tbl sar2130p_qmp_gen3x2_pcie_ep_serdes_tbl[] = {
2861+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x00),
2862+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x06),
2863+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYS_CLK_CTRL, 0x07),
2864+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x07),
2865+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x28),
2866+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x28),
2867+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x0d),
2868+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x0d),
2869+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x00),
2870+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x00),
2871+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x42),
2872+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0xff),
2873+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x04),
2874+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0xff),
2875+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x09),
2876+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x19),
2877+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x14),
2878+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_INTEGLOOP_GAIN0_MODE0, 0xfb),
2879+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_INTEGLOOP_GAIN1_MODE0, 0x03),
2880+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_INTEGLOOP_GAIN0_MODE1, 0xfb),
2881+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_INTEGLOOP_GAIN1_MODE1, 0x03),
2882+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x14),
2883+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x01),
2884+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORECLK_DIV_MODE1, 0x04),
2885+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x16),
2886+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_MODE, 0x14),
2887+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0xa0),
2888+
};
2889+
2890+
static const struct qmp_phy_init_tbl sar2130p_qmp_gen3x2_pcie_ep_pcs_tbl[] = {
2891+
QMP_PHY_INIT_CFG(QPHY_V6_PCS_G12S1_TXDEEMPH_M6DB, 0x17),
2892+
};
2893+
2894+
static const struct qmp_phy_init_tbl sar2130p_qmp_gen3x2_pcie_ep_pcs_misc_tbl[] = {
2895+
QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_EQ_CONFIG1, 0x1e),
2896+
QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_POWER_STATE_CONFIG2, 0x14),
2897+
QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
2898+
};
2899+
28052900
struct qmp_pcie_offsets {
28062901
u16 serdes;
28072902
u16 pcs;
@@ -3392,6 +3487,49 @@ static const struct qmp_phy_cfg msm8998_pciephy_cfg = {
33923487
.skip_start_delay = true,
33933488
};
33943489

3490+
static const struct qmp_phy_cfg sar2130p_qmp_gen3x2_pciephy_cfg = {
3491+
.lanes = 2,
3492+
3493+
.offsets = &qmp_pcie_offsets_v5,
3494+
3495+
.tbls = {
3496+
.tx = sm8550_qmp_gen3x2_pcie_tx_tbl,
3497+
.tx_num = ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_tx_tbl),
3498+
.rx = sm8550_qmp_gen3x2_pcie_rx_tbl,
3499+
.rx_num = ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_rx_tbl),
3500+
.pcs = sm8550_qmp_gen3x2_pcie_pcs_tbl,
3501+
.pcs_num = ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_pcs_tbl),
3502+
.pcs_lane1 = sar2130p_qmp_gen3x2_pcie_pcs_lane1_tbl,
3503+
.pcs_lane1_num = ARRAY_SIZE(sar2130p_qmp_gen3x2_pcie_pcs_lane1_tbl),
3504+
},
3505+
.tbls_rc = &(const struct qmp_phy_cfg_tbls) {
3506+
.serdes = sar2130p_qmp_gen3x2_pcie_rc_serdes_tbl,
3507+
.serdes_num = ARRAY_SIZE(sar2130p_qmp_gen3x2_pcie_rc_serdes_tbl),
3508+
.tx = sar2130p_qmp_gen3x2_pcie_rc_tx_tbl,
3509+
.tx_num = ARRAY_SIZE(sar2130p_qmp_gen3x2_pcie_rc_tx_tbl),
3510+
.pcs = sar2130p_qmp_gen3x2_pcie_rc_pcs_tbl,
3511+
.pcs_num = ARRAY_SIZE(sar2130p_qmp_gen3x2_pcie_rc_pcs_tbl),
3512+
.pcs_misc = sm8550_qmp_gen3x2_pcie_pcs_misc_tbl,
3513+
.pcs_misc_num = ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_pcs_misc_tbl),
3514+
},
3515+
.tbls_ep = &(const struct qmp_phy_cfg_tbls) {
3516+
.serdes = sar2130p_qmp_gen3x2_pcie_ep_serdes_tbl,
3517+
.serdes_num = ARRAY_SIZE(sar2130p_qmp_gen3x2_pcie_ep_serdes_tbl),
3518+
.pcs = sar2130p_qmp_gen3x2_pcie_ep_pcs_tbl,
3519+
.pcs_num = ARRAY_SIZE(sar2130p_qmp_gen3x2_pcie_ep_pcs_tbl),
3520+
.pcs_misc = sar2130p_qmp_gen3x2_pcie_ep_pcs_misc_tbl,
3521+
.pcs_misc_num = ARRAY_SIZE(sar2130p_qmp_gen3x2_pcie_ep_pcs_misc_tbl),
3522+
},
3523+
.reset_list = sdm845_pciephy_reset_l,
3524+
.num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
3525+
.vreg_list = qmp_phy_vreg_l,
3526+
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
3527+
.regs = pciephy_v5_regs_layout,
3528+
3529+
.pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
3530+
.phy_status = PHYSTATUS,
3531+
};
3532+
33953533
static const struct qmp_phy_cfg sc8180x_pciephy_cfg = {
33963534
.lanes = 2,
33973535

@@ -4744,6 +4882,9 @@ static const struct of_device_id qmp_pcie_of_match_table[] = {
47444882
}, {
47454883
.compatible = "qcom,sa8775p-qmp-gen4x4-pcie-phy",
47464884
.data = &sa8775p_qmp_gen4x4_pciephy_cfg,
4885+
}, {
4886+
.compatible = "qcom,sar2130p-qmp-gen3x2-pcie-phy",
4887+
.data = &sar2130p_qmp_gen3x2_pciephy_cfg,
47474888
}, {
47484889
.compatible = "qcom,sc8180x-qmp-pcie-phy",
47494890
.data = &sc8180x_pciephy_cfg,

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