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spi: rockchip: Fix PM runtime count on no-op cs
The early bail out that caused an out-of-bounds write was removed with commit 5c018e3 ("spi: spi-rockchip: Fix out of bounds array access") Unfortunately that caused the PM runtime count to be unbalanced and underflowed on the first call. To fix that reintroduce a no-op check by reading the register directly. Cc: stable@vger.kernel.org Fixes: 5c018e3 ("spi: spi-rockchip: Fix out of bounds array access") Signed-off-by: Christian Loehle <christian.loehle@arm.com> Link: https://patch.msgid.link/1f2b3af4-2b7a-4ac8-ab95-c80120ebf44c@arm.com Signed-off-by: Mark Brown <broonie@kernel.org>
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drivers/spi/spi-rockchip.c

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@@ -241,6 +241,20 @@ static void rockchip_spi_set_cs(struct spi_device *spi, bool enable)
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struct spi_controller *ctlr = spi->controller;
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struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
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bool cs_asserted = spi->mode & SPI_CS_HIGH ? enable : !enable;
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bool cs_actual;
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/*
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* SPI subsystem tries to avoid no-op calls that would break the PM
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* refcount below. It can't however for the first time it is used.
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* To detect this case we read it here and bail out early for no-ops.
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*/
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if (spi_get_csgpiod(spi, 0))
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cs_actual = !!(readl_relaxed(rs->regs + ROCKCHIP_SPI_SER) & 1);
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else
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cs_actual = !!(readl_relaxed(rs->regs + ROCKCHIP_SPI_SER) &
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BIT(spi_get_chipselect(spi, 0)));
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if (unlikely(cs_actual == cs_asserted))
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return;
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if (cs_asserted) {
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/* Keep things powered as long as CS is asserted */

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