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geertugeertu
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pinctrl: renesas: r8a779g0: FIX PWM suffixes
PWM channels 0, 2, 8, and 9 do not have alternate pins. Remove their "_a" or "_b" suffixes to increase uniformity. Fixes: c606c2f ("pinctrl: renesas: r8a779g0: Add missing PWM") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/abb748e6e1e4e7d78beac7d96e7a0a3481b32e75.1717754960.git.geert+renesas@glider.be
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-40
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‎drivers/pinctrl/renesas/pfc-r8a779g0.c

Lines changed: 36 additions & 40 deletions
Original file line numberDiff line numberDiff line change
@@ -316,9 +316,9 @@
316316
#define IP1SR1_11_8 FM(MSIOF0_SCK) FM(HSCK1_B) FM(SCK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
317317
#define IP1SR1_15_12 FM(MSIOF0_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
318318
#define IP1SR1_19_16 FM(HTX0) FM(TX0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
319-
#define IP1SR1_23_20 FM(HCTS0_N) FM(CTS0_N) FM(PWM8_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
320-
#define IP1SR1_27_24 FM(HRTS0_N) FM(RTS0_N) FM(PWM9_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
321-
#define IP1SR1_31_28 FM(HSCK0) FM(SCK0) FM(PWM0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
319+
#define IP1SR1_23_20 FM(HCTS0_N) FM(CTS0_N) FM(PWM8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
320+
#define IP1SR1_27_24 FM(HRTS0_N) FM(RTS0_N) FM(PWM9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
321+
#define IP1SR1_31_28 FM(HSCK0) FM(SCK0) FM(PWM0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
322322

323323
/* IP2SR1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
324324
#define IP2SR1_3_0 FM(HRX0) FM(RX0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
@@ -355,7 +355,7 @@
355355
#define IP1SR2_15_12 FM(CANFD0_RX) FM(STPWT_EXTFXR) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
356356
#define IP1SR2_19_16 FM(CANFD2_TX) FM(TPU0TO2) F_(0, 0) FM(TCLK3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
357357
#define IP1SR2_23_20 FM(CANFD2_RX) FM(TPU0TO3) FM(PWM1_B) FM(TCLK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
358-
#define IP1SR2_27_24 FM(CANFD3_TX) F_(0, 0) FM(PWM2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
358+
#define IP1SR2_27_24 FM(CANFD3_TX) F_(0, 0) FM(PWM2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
359359
#define IP1SR2_31_28 FM(CANFD3_RX) F_(0, 0) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
360360

361361
/* IP2SR2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
@@ -827,15 +827,15 @@ static const u16 pinmux_data[] = {
827827

828828
PINMUX_IPSR_GPSR(IP1SR1_23_20, HCTS0_N),
829829
PINMUX_IPSR_GPSR(IP1SR1_23_20, CTS0_N),
830-
PINMUX_IPSR_GPSR(IP1SR1_23_20, PWM8_A),
830+
PINMUX_IPSR_GPSR(IP1SR1_23_20, PWM8),
831831

832832
PINMUX_IPSR_GPSR(IP1SR1_27_24, HRTS0_N),
833833
PINMUX_IPSR_GPSR(IP1SR1_27_24, RTS0_N),
834-
PINMUX_IPSR_GPSR(IP1SR1_27_24, PWM9_A),
834+
PINMUX_IPSR_GPSR(IP1SR1_27_24, PWM9),
835835

836836
PINMUX_IPSR_GPSR(IP1SR1_31_28, HSCK0),
837837
PINMUX_IPSR_GPSR(IP1SR1_31_28, SCK0),
838-
PINMUX_IPSR_GPSR(IP1SR1_31_28, PWM0_A),
838+
PINMUX_IPSR_GPSR(IP1SR1_31_28, PWM0),
839839

840840
/* IP2SR1 */
841841
PINMUX_IPSR_GPSR(IP2SR1_3_0, HRX0),
@@ -937,7 +937,7 @@ static const u16 pinmux_data[] = {
937937
PINMUX_IPSR_GPSR(IP1SR2_23_20, TCLK4_A),
938938

939939
PINMUX_IPSR_GPSR(IP1SR2_27_24, CANFD3_TX),
940-
PINMUX_IPSR_GPSR(IP1SR2_27_24, PWM2_B),
940+
PINMUX_IPSR_GPSR(IP1SR2_27_24, PWM2),
941941

942942
PINMUX_IPSR_GPSR(IP1SR2_31_28, CANFD3_RX),
943943
PINMUX_IPSR_GPSR(IP1SR2_31_28, PWM3_B),
@@ -2090,13 +2090,13 @@ static const unsigned int pcie1_clkreq_n_mux[] = {
20902090
PCIE1_CLKREQ_N_MARK,
20912091
};
20922092

2093-
/* - PWM0_A ------------------------------------------------------------------- */
2094-
static const unsigned int pwm0_a_pins[] = {
2095-
/* PWM0_A */
2093+
/* - PWM0 ------------------------------------------------------------------- */
2094+
static const unsigned int pwm0_pins[] = {
2095+
/* PWM0 */
20962096
RCAR_GP_PIN(1, 15),
20972097
};
2098-
static const unsigned int pwm0_a_mux[] = {
2099-
PWM0_A_MARK,
2098+
static const unsigned int pwm0_mux[] = {
2099+
PWM0_MARK,
21002100
};
21012101

21022102
/* - PWM1_A ------------------------------------------------------------------- */
@@ -2117,13 +2117,13 @@ static const unsigned int pwm1_b_mux[] = {
21172117
PWM1_B_MARK,
21182118
};
21192119

2120-
/* - PWM2_B ------------------------------------------------------------------- */
2121-
static const unsigned int pwm2_b_pins[] = {
2122-
/* PWM2_B */
2120+
/* - PWM2 ------------------------------------------------------------------- */
2121+
static const unsigned int pwm2_pins[] = {
2122+
/* PWM2 */
21232123
RCAR_GP_PIN(2, 14),
21242124
};
2125-
static const unsigned int pwm2_b_mux[] = {
2126-
PWM2_B_MARK,
2125+
static const unsigned int pwm2_mux[] = {
2126+
PWM2_MARK,
21272127
};
21282128

21292129
/* - PWM3_A ------------------------------------------------------------------- */
@@ -2180,22 +2180,22 @@ static const unsigned int pwm7_mux[] = {
21802180
PWM7_MARK,
21812181
};
21822182

2183-
/* - PWM8_A ------------------------------------------------------------------- */
2184-
static const unsigned int pwm8_a_pins[] = {
2185-
/* PWM8_A */
2183+
/* - PWM8 ------------------------------------------------------------------- */
2184+
static const unsigned int pwm8_pins[] = {
2185+
/* PWM8 */
21862186
RCAR_GP_PIN(1, 13),
21872187
};
2188-
static const unsigned int pwm8_a_mux[] = {
2189-
PWM8_A_MARK,
2188+
static const unsigned int pwm8_mux[] = {
2189+
PWM8_MARK,
21902190
};
21912191

2192-
/* - PWM9_A ------------------------------------------------------------------- */
2193-
static const unsigned int pwm9_a_pins[] = {
2194-
/* PWM9_A */
2192+
/* - PWM9 ------------------------------------------------------------------- */
2193+
static const unsigned int pwm9_pins[] = {
2194+
/* PWM9 */
21952195
RCAR_GP_PIN(1, 14),
21962196
};
2197-
static const unsigned int pwm9_a_mux[] = {
2198-
PWM9_A_MARK,
2197+
static const unsigned int pwm9_mux[] = {
2198+
PWM9_MARK,
21992199
};
22002200

22012201
/* - QSPI0 ------------------------------------------------------------------ */
@@ -2658,18 +2658,18 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
26582658
SH_PFC_PIN_GROUP(pcie0_clkreq_n),
26592659
SH_PFC_PIN_GROUP(pcie1_clkreq_n),
26602660

2661-
SH_PFC_PIN_GROUP(pwm0_a), /* suffix might be updated */
2661+
SH_PFC_PIN_GROUP(pwm0),
26622662
SH_PFC_PIN_GROUP(pwm1_a),
26632663
SH_PFC_PIN_GROUP(pwm1_b),
2664-
SH_PFC_PIN_GROUP(pwm2_b), /* suffix might be updated */
2664+
SH_PFC_PIN_GROUP(pwm2),
26652665
SH_PFC_PIN_GROUP(pwm3_a),
26662666
SH_PFC_PIN_GROUP(pwm3_b),
26672667
SH_PFC_PIN_GROUP(pwm4),
26682668
SH_PFC_PIN_GROUP(pwm5),
26692669
SH_PFC_PIN_GROUP(pwm6),
26702670
SH_PFC_PIN_GROUP(pwm7),
2671-
SH_PFC_PIN_GROUP(pwm8_a), /* suffix might be updated */
2672-
SH_PFC_PIN_GROUP(pwm9_a), /* suffix might be updated */
2671+
SH_PFC_PIN_GROUP(pwm8),
2672+
SH_PFC_PIN_GROUP(pwm9),
26732673

26742674
SH_PFC_PIN_GROUP(qspi0_ctrl),
26752675
BUS_DATA_PIN_GROUP(qspi0_data, 2),
@@ -2923,8 +2923,7 @@ static const char * const pcie_groups[] = {
29232923
};
29242924

29252925
static const char * const pwm0_groups[] = {
2926-
/* suffix might be updated */
2927-
"pwm0_a",
2926+
"pwm0",
29282927
};
29292928

29302929
static const char * const pwm1_groups[] = {
@@ -2933,8 +2932,7 @@ static const char * const pwm1_groups[] = {
29332932
};
29342933

29352934
static const char * const pwm2_groups[] = {
2936-
/* suffix might be updated */
2937-
"pwm2_b",
2935+
"pwm2",
29382936
};
29392937

29402938
static const char * const pwm3_groups[] = {
@@ -2959,13 +2957,11 @@ static const char * const pwm7_groups[] = {
29592957
};
29602958

29612959
static const char * const pwm8_groups[] = {
2962-
/* suffix might be updated */
2963-
"pwm8_a",
2960+
"pwm8",
29642961
};
29652962

29662963
static const char * const pwm9_groups[] = {
2967-
/* suffix might be updated */
2968-
"pwm9_a",
2964+
"pwm9",
29692965
};
29702966

29712967
static const char * const qspi0_groups[] = {

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