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MUX gate #6

@send2cny

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@send2cny

I tried to implement MUX gate with using this new MK algo.
There is no issue with AND, ANDNY and OR gates.

But errors appears when directly pass u1 and u2 over OR gates.
Errors are not consistence via different trials.
example passing 1, 1, 1, into MUX
sometime, we get logic 0, sometime we get logic 1.

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