Skip to content
This repository was archived by the owner on May 7, 2025. It is now read-only.

Commit 0f9b784

Browse files
author
cesare
committed
v2.2.8
- fix issue #4: incorrect irq routing of plic sources > 31 - hexfive-conf@95470e - hexfive-kern@7fcd98 - minor non-functional changes to zones - update README.md url links to 2.2.8
1 parent 866465a commit 0f9b784

File tree

15 files changed

+94
-49
lines changed

15 files changed

+94
-49
lines changed

‎.settings/language.settings.xml

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3,7 +3,7 @@
33
<configuration id="cdt.managedbuild.toolchain.gnu.cross.base.1316478169" name="X300">
44
<extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
55
<provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
6-
<provider class="org.eclipse.cdt.internal.build.crossgcc.CrossGCCBuiltinSpecsDetector" console="false" env-hash="1488632332492422240" id="org.eclipse.cdt.build.crossgcc.CrossGCCBuiltinSpecsDetector" keep-relative-paths="false" name="CDT Cross GCC Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} -march=rv32imac -mabi=ilp32 -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true">
6+
<provider class="org.eclipse.cdt.internal.build.crossgcc.CrossGCCBuiltinSpecsDetector" console="false" env-hash="1486074240399614240" id="org.eclipse.cdt.build.crossgcc.CrossGCCBuiltinSpecsDetector" keep-relative-paths="false" name="CDT Cross GCC Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} -march=rv32imac -mabi=ilp32 -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true">
77
<language-scope id="org.eclipse.cdt.core.gcc"/>
88
<language-scope id="org.eclipse.cdt.core.g++"/>
99
</provider>

‎README.md

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -30,9 +30,9 @@ For instructions on how to upload the bitstream to the ARTY board and how to con
3030

3131
Prebuilt fpga bitstreams including the X300 RISC-V SoC and the MultiZone Trusted Firmware are provided as release assets ready to go:
3232

33-
- [multizone-iot-sdk-arty-35t.mcs](https://github.com/hex-five/multizone-iot-sdk/releases/download/v2.2.7/multizone-iot-sdk-arty-35t.mcs)
33+
- [multizone-iot-sdk-arty-35t.mcs](https://github.com/hex-five/multizone-iot-sdk/releases/download/v2.2.8/multizone-iot-sdk-arty-35t.mcs)
3434

35-
- [multizone-iot-sdk-arty-100t.mcs](https://github.com/hex-five/multizone-iot-sdk/releases/download/v2.2.7/multizone-iot-sdk-arty-100t.mcs)
35+
- [multizone-iot-sdk-arty-100t.mcs](https://github.com/hex-five/multizone-iot-sdk/releases/download/v2.2.8/multizone-iot-sdk-arty-100t.mcs)
3636

3737
If you are impatient to run the MultiZone Trusted Firmware demo, just upload the right bitstream to your Arty board and skip all steps below. For this you only need [Xilinx Vivado Lab](https://www.xilinx.com/support/download.html) an the instructions at https://github.com/hex-five/multizone-fpga#readme
3838

‎bsp/X300/memory.ods

7 Bytes
Binary file not shown.

‎bsp/X300/multizone.cfg

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -21,14 +21,14 @@ Zone = 2
2121

2222
Zone = 3
2323
irq = 16, 17, 18 # BTN0 BTN1 BTN2 (CLINT)
24-
base = 0x20406800; size = 2K; rwx = rx # FLASH
24+
base = 0x20406800; size = 4K; rwx = rx # FLASH
2525
base = 0x8000E800; size = 2K; rwx = rw # RAM
2626
base = 0x8000A800; size = 4K; rwx = rx # SH BUFF1
2727
base = 0x10012000; size = 0x100; rwx = rw # GPIO
2828
base = 0x10025000; size = 0x100; rwx = rw # PWM LED
2929

3030
Zone = 4
31-
base = 0x20407000; size = 8K; rwx = rx # FLASH
31+
base = 0x20407800; size = 8K; rwx = rx # FLASH
3232
base = 0x8000F000; size = 4K; rwx = rw # RAM
3333
base = 0x8000B800; size = 8K; rwx = rx # SH BUFF2
3434
base = 0x10012000; size = 0x100; rwx = rw # GPIO

‎bsp/X300/newlib/crt0.S

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -7,6 +7,12 @@
77
_start:
88
.cfi_startproc
99
.cfi_undefined ra
10+
11+
/* setup trap vector */
12+
la a0, _mtvec
13+
csrw mtvec, a0
14+
csrs mtvec, 1
15+
1016
.option push
1117
.option norelax
1218
la gp, __global_pointer$
@@ -64,3 +70,5 @@ _init: ret
6470
.type _fini, @function
6571
_fini: ret
6672
.size _fini, .-_fini
73+
74+
.include "mtvec.s"

‎bsp/X300/newlib/mtvec.s

Lines changed: 55 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,55 @@
1+
/* Copyright(C) 2020 Hex Five Security, Inc. - All Rights Reserved */
2+
3+
.align 2
4+
5+
_mtvec:
6+
7+
.option push
8+
.option norvc
9+
10+
irq0: j trp_isr
11+
irq1: j .
12+
irq2: j .
13+
irq3: j msi_isr
14+
irq4: j .
15+
irq5: j .
16+
irq6: j .
17+
irq7: j tmr_isr
18+
irq8: j .
19+
irq9: j .
20+
irq10: j .
21+
irq11: j plic_isr
22+
irq12: j .
23+
irq13: j .
24+
irq14: j .
25+
irq15: j .
26+
irq16: j btn0_isr
27+
irq17: j btn1_isr
28+
irq18: j btn2_isr
29+
irq19: j dma_isr
30+
irq20: j .
31+
irq21: j .
32+
irq22: j .
33+
irq23: j .
34+
irq24: j .
35+
irq25: j .
36+
irq26: j .
37+
irq27: j .
38+
irq28: j .
39+
irq29: j .
40+
irq30: j .
41+
irq31: j .
42+
43+
.option pop
44+
45+
.weak trp_isr, msi_isr, tmr_isr, dma_isr, plic_isr, btn0_isr, btn1_isr, btn2_isr
46+
47+
trp_isr:
48+
msi_isr:
49+
tmr_isr:
50+
dma_isr:
51+
plic_isr:
52+
btn0_isr:
53+
btn1_isr:
54+
btn2_isr:
55+
j .

‎bsp/X300/newlib/newlib.mk

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -7,6 +7,7 @@ ASM_SRCS += $(NEWLIB_DIR)/crt0.S
77
C_SRCS += $(NEWLIB_DIR)/newlib.c
88
C_SRCS += $(PLATFORM_DIR)/xemaclite.c
99

10+
INCLUDES += -I$(NEWLIB_DIR)
1011
INCLUDES += -I$(PLATFORM_DIR)
1112

1213
LDFLAGS += -T $(PLATFORM_DIR)/memory.lds

‎ext/liblwip.a

-4 Bytes
Binary file not shown.

‎ext/multizone/multizone.jar

490 Bytes
Binary file not shown.

‎zone1/main.c

Lines changed: 5 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -85,8 +85,7 @@ static volatile char inbox[4][16] = { {'\0'}, {'\0'}, {'\0'}, {'\0'} };
8585
typedef enum {zone1=1, zone2, zone3, zone4} Zone;
8686

8787
// ----------------------------------------------------------------------------
88-
static void (*trap_vect[__riscv_xlen])(void) = {};
89-
__attribute__((interrupt())) void trp_handler(void) { // non maskable traps
88+
__attribute__((interrupt())) void trp_isr(void) { // non maskable traps
9089

9190
/* const unsigned long mcause = MZONE_CSRR(CSR_MCAUSE);
9291
const unsigned long mepc = MZONE_CSRR(CSR_MEPC);
@@ -134,7 +133,7 @@ __attribute__((interrupt())) void trp_handler(void) { // non maskable traps
134133
for( ;; );
135134

136135
}
137-
__attribute__((interrupt())) void msi_handler(void) { // machine software interrupt (3)
136+
__attribute__((interrupt())) void msi_isr(void) { // machine software interrupt (3)
138137

139138
for (Zone zone = zone1; zone <= zone4; zone++) {
140139
char msg[16];
@@ -143,10 +142,10 @@ __attribute__((interrupt())) void msi_handler(void) { // machine software inter
143142
}
144143

145144
}
146-
__attribute__((interrupt())) void tmr_handler(void) { // machine timer interrupt (7)
145+
__attribute__((interrupt())) void tmr_isr(void) { // machine timer interrupt (7)
147146
MZONE_WRTIMECMP((uint64_t)-1); // clear mip.7
148147
}
149-
__attribute__((interrupt())) void plic_handler(void) { // machine external interrupt (11)
148+
__attribute__((interrupt())) void plic_isr(void) { // machine external interrupt (11)
150149

151150
const uint32_t plic_int = PLIC_REG(PLIC_CLAIM); // PLIC claim
152151

@@ -253,13 +252,6 @@ int main(void) {
253252
//while(1) MZONE_YIELD();
254253
//while(1);
255254

256-
// setup vectored trap handler
257-
trap_vect[0] = trp_handler;
258-
trap_vect[3] = msi_handler;
259-
trap_vect[7] = tmr_handler;
260-
trap_vect[11] = plic_handler;
261-
CSRW(mtvec, trap_vect); CSRS(mtvec, 0x1);
262-
263255
// enable msip/inbox interrupt
264256
CSRS(mie, 1<<3);
265257

@@ -269,7 +261,7 @@ int main(void) {
269261
// enable XEMACLITE RX IRQ (PLIC Priority 1=lowest 7=highest)
270262
CSRS(mie, 1<<11); // enable external interrupts (PLIC/XEMAC)
271263
PLIC_REG(PLIC_PRI + (PLIC_SRC_XEMAC << PLIC_SHIFT_PER_SRC)) = 1;
272-
PLIC_REG(PLIC_EN) |= 1 << PLIC_SRC_XEMAC;
264+
PLIC_REG(PLIC_EN + 4*(PLIC_SRC_XEMAC/32)) |= 1 << (PLIC_SRC_XEMAC%32);
273265

274266
// enable global interrupt
275267
CSRS(mstatus, 1<<3);

‎zone2/main.c

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -31,7 +31,7 @@ int inbox_empty(void){
3131
return (inbox[0][0]=='\0' && inbox[1][0]=='\0' && inbox[2][0]=='\0' && inbox[3][0]=='\0');
3232
}
3333

34-
__attribute__(( interrupt())) void trap_handler(void){
34+
__attribute__(( interrupt())) void trp_isr(void){
3535

3636
const unsigned long mcause = MZONE_CSRR(CSR_MCAUSE);
3737
const unsigned long mepc = MZONE_CSRR(CSR_MEPC);
@@ -640,8 +640,8 @@ int main (void) {
640640
//while(1) MZONE_YIELD();
641641
//while(1);
642642

643-
// setup trap handler
644-
CSRW(mtvec, trap_handler); // register trap handler
643+
// set trap mode "direct"
644+
CSRC(mtvec, 1);
645645

646646
// enable interrupt sources
647647
CSRS(mie, 1<<3);
@@ -650,7 +650,7 @@ int main (void) {
650650
// Enable PLIC source Priority 2, 1=lowest 7=highest)
651651
CSRS(mie, 1<<11);
652652
PLIC_REG(PLIC_PRI + (PLIC_SRC_UART << PLIC_SHIFT_PER_SRC)) = 2;
653-
PLIC_REG(PLIC_EN) |= 1 << PLIC_SRC_UART;
653+
PLIC_REG(PLIC_EN + 4*(PLIC_SRC_UART/32)) |= 1 << (PLIC_SRC_UART%32);
654654

655655
// enable global interrupt
656656
CSRS(mstatus, 1<<3);

‎zone3.1/main.c

Lines changed: 6 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -21,8 +21,7 @@ typedef enum {zone1=1, zone2, zone3, zone4} Zone;
2121
static volatile char inbox[4][16] = { {'\0'}, {'\0'}, {'\0'}, {'\0'} };
2222

2323
// ----------------------------------------------------------------------------
24-
static void (*trap_vect[__riscv_xlen])(void) = {};
25-
__attribute__((interrupt())) void trp_handler(void) { // trap handler (0)
24+
__attribute__((interrupt())) void trp_isr(void) { // trap handler (0)
2625

2726
asm volatile("ebreak");
2827

@@ -40,7 +39,7 @@ __attribute__((interrupt())) void trp_handler(void) { // trap handler (0)
4039
}*/
4140

4241
}
43-
__attribute__((interrupt())) void msi_handler(void) { // machine software interrupt (3)
42+
__attribute__((interrupt())) void msi_isr(void) { // machine software interrupt (3)
4443

4544
for (Zone zone = zone1; zone <= zone4; zone++) {
4645
char msg[16];
@@ -49,7 +48,7 @@ __attribute__((interrupt())) void msi_handler(void) { // machine software inter
4948
}
5049

5150
}
52-
__attribute__((interrupt())) void tmr_handler(void) { // machine timer interrupt (7)
51+
__attribute__((interrupt())) void tmr_isr(void) { // machine timer interrupt (7)
5352

5453
static uint16_t r=0x3F;
5554
static uint16_t g=0;
@@ -67,7 +66,7 @@ __attribute__((interrupt())) void tmr_handler(void) { // machine timer interrup
6766
MZONE_ADTIMECMP((uint64_t)25*RTC_FREQ/1000);
6867

6968
}
70-
__attribute__((interrupt())) void btn0_handler(void) {
69+
__attribute__((interrupt())) void btn0_isr(void) {
7170

7271
static uint64_t debounce = 0;
7372
const uint64_t T = MZONE_RDTIME();
@@ -81,7 +80,7 @@ __attribute__((interrupt())) void btn0_handler(void) {
8180
GPIO_REG(GPIO_HIGH_IP) |= (1<<BTN0); //clear gpio irq
8281

8382
}
84-
__attribute__((interrupt())) void btn1_handler(void) {
83+
__attribute__((interrupt())) void btn1_isr(void) {
8584

8685
static uint64_t debounce = 0;
8786
const uint64_t T = MZONE_RDTIME();
@@ -95,7 +94,7 @@ __attribute__((interrupt())) void btn1_handler(void) {
9594
GPIO_REG(GPIO_HIGH_IP) |= (1<<BTN1); //clear gpio irq
9695

9796
}
98-
__attribute__((interrupt())) void btn2_handler(void) {
97+
__attribute__((interrupt())) void btn2_isr(void) {
9998

10099
static uint64_t debounce = 0;
101100
const uint64_t T = MZONE_RDTIME();
@@ -171,16 +170,6 @@ int main (void){
171170
//while(1) MZONE_YIELD();
172171
//while(1);
173172

174-
// setup vectored trap handler
175-
trap_vect[0] = trp_handler;
176-
trap_vect[3] = msi_handler;
177-
trap_vect[7] = tmr_handler;
178-
trap_vect[BTN0_IRQ] = btn0_handler;
179-
trap_vect[BTN1_IRQ] = btn1_handler;
180-
trap_vect[BTN2_IRQ] = btn2_handler;
181-
CSRW(mtvec, trap_vect);
182-
CSRS(mtvec, 0x1);
183-
184173
// setup peripherals
185174
PWM_REG(PWM_CFG) = (PWM_CFG_ENALWAYS | PWM_CFG_ZEROCMP);
186175
PWM_REG(PWM_CMP0) = 0xFE;

‎zone3/linker.lds

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -5,8 +5,8 @@ OUTPUT_ARCH( "riscv" )
55
ENTRY( _start )
66

77
MEMORY {
8-
flash (rxai!w) : ORIGIN = flash + 0x6800, LENGTH = 2K
9-
prog (rxai!w) : ORIGIN = flash + 0x6800, LENGTH = 2K
8+
flash (rxai!w) : ORIGIN = flash + 0x6800, LENGTH = 4K
9+
prog (rxai!w) : ORIGIN = flash + 0x6800, LENGTH = 4K
1010
ram (wa!xri) : ORIGIN = dtim + 0xE800, LENGTH = 2K
1111
}
1212

‎zone4.1/main.c

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -165,7 +165,7 @@ uint64_t led_off_task(){ // LED off
165165
return UINT64_MAX;
166166
}
167167

168-
__attribute__(( interrupt())) void trap_handler(void){
168+
__attribute__(( interrupt())) void trp_isr(void){
169169

170170
#define IRQ ( 1UL<< (__riscv_xlen-1) )
171171

@@ -247,10 +247,10 @@ int main (void){
247247
GPIO_REG(GPIO_OUTPUT_EN) |= (1 << SPI_TCK | 1<< SPI_TDO | 1 << LED_RED | 1 << LED_GRN );
248248
GPIO_REG(GPIO_DRIVE) |= (1 << SPI_TCK | 1<< SPI_TDO );
249249

250-
CSRW(mtvec, trap_handler); // register trap handler
251-
CSRS(mie, 1<<3); // enable msip/inbox interrupt
252-
CSRS(mie, 1<<7); // enable timer interrupts
253-
CSRS(mstatus, 1<<3); // enable global interrupts
250+
CSRC(mtvec, 1); // set trap mode "direct"
251+
CSRS(mie, 1<<3); // enable msip/inbox interrupt
252+
CSRS(mie, 1<<7); // enable timer interrupts
253+
CSRS(mstatus, 1<<3); // enable global interrupts
254254

255255
// Start task2: Hartbeat LED, USB status, Keep alive pkt
256256
timer_set(KEEP_ALIVE_TASK, 0);

‎zone4/linker.lds

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -5,8 +5,8 @@ OUTPUT_ARCH( "riscv" )
55
ENTRY( _start )
66

77
MEMORY {
8-
flash (rxai!w) : ORIGIN = flash + 0x7000, LENGTH = 8K
9-
prog (rxai!w) : ORIGIN = flash + 0x7000, LENGTH = 8K
8+
flash (rxai!w) : ORIGIN = flash + 0x7800, LENGTH = 8K
9+
prog (rxai!w) : ORIGIN = flash + 0x7800, LENGTH = 8K
1010
ram (wa!xri) : ORIGIN = dtim + 0xF000, LENGTH = 4K
1111
}
1212

@@ -158,4 +158,4 @@ SECTIONS {
158158
PROVIDE( __heap_end = . );
159159
} >ram AT>ram
160160

161-
}
161+
}

0 commit comments

Comments
 (0)