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bruno-f-cruzbruno-f-cruz
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Merge pull request #2 from harp-tech/bc-interface-autogen
Add initial schema and automatic interface generation
2 parents 1d2baaa + 6579cef commit 3e3ffa5

21 files changed

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lines changed

‎.editorconfig

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# To learn more about .editorconfig see https://aka.ms/editorconfigdocs
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###############################
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# Core EditorConfig Options #
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###############################
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# All files
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[*]
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indent_style = space
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# XML project files
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[*.{csproj,vcxproj,vcxproj.filters,proj,projitems,shproj,bonsai}]
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indent_size = 2
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# XML config files
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[*.{props,targets,ruleset,config,nuspec,resx,vsixmanifest,vsct}]
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indent_size = 2
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# Code files
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[*.{cs,csx}]
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indent_size = 4
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insert_final_newline = true
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charset = utf-8-bom
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###############################
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# .NET Coding Conventions #
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###############################
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[*.{cs}]
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# Organize usings
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dotnet_sort_system_directives_first = true

‎.gitignore

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desktop.ini
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# Visual studio files
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.vs
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.suo
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.nuget
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bin
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obj
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Debug
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packages
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**/Debug
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*.atsuo
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*.user
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*-preview*.hex
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*.componentinfo.xml

‎Assets/pcb.png

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‎Firmware/.gitignore

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# Visual studio files
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.vs
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.suo
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.nuget
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bin
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obj
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Debug
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packages
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*.componentinfo.xml

‎Firmware/AnalogInput/AnalogInput.cppproj

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@@ -118,8 +118,6 @@
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</avrgcccpp.linker.libraries.Libraries>
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<avrgcccpp.linker.libraries.LibrarySearchPaths>
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<ListValues>
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<Value>C:\Users\Filipe Carvalho\Documents\BitBucket\Device.LoadCells\Firmware\LoadCells</Value>
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<Value>C:\Users\OEPS\Documents\github\harp-tech\harp_analog_input\Firmware\AnalogInput</Value>
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</ListValues>
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</avrgcccpp.linker.libraries.LibrarySearchPaths>
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<avrgcccpp.assembler.general.IncludePaths>
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</avrgcccpp.linker.libraries.Libraries>
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<avrgcccpp.linker.libraries.LibrarySearchPaths>
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<ListValues>
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<Value>C:\Users\Filipe Carvalho\Documents\BitBucket\Device.LoadCells\Firmware\LoadCells</Value>
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<Value>C:\Users\OEPS\Documents\github\harp-tech\harp_analog_input\Firmware\AnalogInput</Value>
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<Value>..</Value>
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</ListValues>
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</avrgcccpp.linker.libraries.LibrarySearchPaths>
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<avrgcccpp.assembler.general.IncludePaths>

‎Firmware/AnalogInput/app.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -200,7 +200,7 @@ void core_callback_t_500us(void)
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if (app_regs.REG_SAMPLE_FREQUENCY == GM_2KHZ)
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{
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core_func_mark_user_timestamp();
203-
set_CONVST;
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set_CONVSTA;
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set_CONVSTB;
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switch (app_regs.REG_TRIGGER_DESTINY)
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{
@@ -234,7 +234,7 @@ void core_callback_t_1ms(void)
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if (app_regs.REG_START)
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{
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core_func_mark_user_timestamp();
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set_CONVST;
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set_CONVSTA;
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set_CONVSTB;
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switch (app_regs.REG_TRIGGER_DESTINY)
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{

‎Firmware/AnalogInput/app_ios_and_regs.c

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -16,13 +16,13 @@ void init_ios(void)
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io_set_int(&PORTD, INT_LEVEL_LOW, 0, (1<<1), false); // BUSY
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1818
/* Configure output pins */
19-
io_pin2out(&PORTB, 1, OUT_IO_DIGITAL, IN_EN_IO_EN); // DO3
20-
io_pin2out(&PORTA, 0, OUT_IO_DIGITAL, IN_EN_IO_EN); // DO2
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io_pin2out(&PORTA, 0, OUT_IO_DIGITAL, IN_EN_IO_EN); // DO0
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io_pin2out(&PORTA, 1, OUT_IO_DIGITAL, IN_EN_IO_EN); // DO1
22-
io_pin2out(&PORTA, 2, OUT_IO_DIGITAL, IN_EN_IO_EN); // DO0
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io_pin2out(&PORTA, 2, OUT_IO_DIGITAL, IN_EN_IO_EN); // DO2
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io_pin2out(&PORTA, 3, OUT_IO_DIGITAL, IN_EN_IO_EN); // DO3
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io_pin2out(&PORTC, 4, OUT_IO_DIGITAL, IN_EN_IO_EN); // CS_ADC
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io_pin2out(&PORTC, 0, OUT_IO_DIGITAL, IN_EN_IO_EN); // CONVSTA
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io_pin2out(&PORTC, 1, OUT_IO_DIGITAL, IN_EN_IO_EN); // CONVSTB
25-
io_pin2out(&PORTC, 4, OUT_IO_DIGITAL, IN_EN_IO_EN); // CS_ADC
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io_pin2out(&PORTC, 5, OUT_IO_DIGITAL, IN_EN_IO_DIS); // MOSI
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io_pin2out(&PORTC, 7, OUT_IO_DIGITAL, IN_EN_IO_DIS); // SCK
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io_pin2out(&PORTD, 0, OUT_IO_WIREDAND, IN_EN_IO_EN); // RESET
@@ -32,12 +32,12 @@ void init_ios(void)
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io_pin2out(&PORTA, 4, OUT_IO_DIGITAL, IN_EN_IO_EN); // RANGE
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3434
/* Initialize output pins */
35-
clr_DO3;
36-
clr_DO2;
37-
clr_DO1;
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clr_DO0;
36+
clr_DO1;
37+
clr_DO2;
38+
clr_DO3;
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set_CS_ADC;
40-
clr_CONVST;
40+
clr_CONVSTA;
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clr_CONVSTB;
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clr_MOSI;
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clr_SCK;

‎Firmware/AnalogInput/app_ios_and_regs.h

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Original file line numberDiff line numberDiff line change
@@ -17,12 +17,13 @@ void init_ios(void);
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/************************************************************************/
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/* Definition of output pins */
1919
/************************************************************************/
20-
// DO3 Description: Output DO0
21-
// DO2 Description: Output DO1
22-
// DO1 Description: Output DO2
23-
// DO0 Description: Output DO3
20+
// DO0 Description: Output DO0
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// DO1 Description: Output DO1
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// DO2 Description: Output DO2
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// DO3 Description: Output DO3
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// CS_ADC Description: Chip select
25-
// CONVST Description: Convert
25+
// CONVSTA Description: Convert
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// CONVSTB Description: Convert
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// MOSI Description: Serial data input
2728
// SCK Description: Serial data clock
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// RESET Description: Reset
@@ -31,49 +32,48 @@ void init_ios(void);
3132
// OS2 Description: Oversampling bit 2
3233
// RANGE Description: Selects range 5 or 10V
3334

34-
/* DO3 */
35-
#define set_DO3 set_io(PORTB, 1)
36-
#define clr_DO3 clear_io(PORTB, 1)
37-
#define tgl_DO3 toggle_io(PORTB, 1)
38-
#define read_DO3 read_io(PORTB, 1)
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40-
/* DO2 */
41-
#define set_DO2 set_io(PORTA, 0)
42-
#define clr_DO2 clear_io(PORTA, 0)
43-
#define tgl_DO2 toggle_io(PORTA, 0)
44-
#define read_DO2 read_io(PORTA, 0)
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/* DO0 */
36+
#define set_DO0 set_io(PORTA, 0)
37+
#define clr_DO0 clear_io(PORTA, 0)
38+
#define tgl_DO0 toggle_io(PORTA, 0)
39+
#define read_DO0 read_io(PORTA, 0)
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4641
/* DO1 */
4742
#define set_DO1 set_io(PORTA, 1)
4843
#define clr_DO1 clear_io(PORTA, 1)
4944
#define tgl_DO1 toggle_io(PORTA, 1)
5045
#define read_DO1 read_io(PORTA, 1)
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52-
/* DO0 */
53-
#define set_DO0 set_io(PORTA, 2)
54-
#define clr_DO0 clear_io(PORTA, 2)
55-
#define tgl_DO0 toggle_io(PORTA, 2)
56-
#define read_DO0 read_io(PORTA, 2)
47+
/* DO2 */
48+
#define set_DO2 set_io(PORTA, 2)
49+
#define clr_DO2 clear_io(PORTA, 2)
50+
#define tgl_DO2 toggle_io(PORTA, 2)
51+
#define read_DO2 read_io(PORTA, 2)
52+
53+
/* DO3 */
54+
#define set_DO3 set_io(PORTA, 3)
55+
#define clr_DO3 clear_io(PORTA, 3)
56+
#define tgl_DO3 toggle_io(PORTA, 3)
57+
#define read_DO3 read_io(PORTA, 3)
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5859
/* CS_ADC */
59-
#define set_CS_ADC clear_io(PORTC, 4)
60+
#define set_CS_ADC clear_io(PORTC, 4)
6061
#define clr_CS_ADC set_io(PORTC, 4)
6162
#define tgl_CS_ADC toggle_io(PORTC, 4)
6263
#define read_CS_ADC read_io(PORTC, 4)
6364

6465
/* CONVSTA */
65-
#define set_CONVST set_io(PORTC, 0)
66-
#define clr_CONVST clear_io(PORTC, 0)
67-
#define tgl_CONVST toggle_io(PORTC, 0)
68-
#define read_CONVST read_io(PORTC, 0)
66+
#define set_CONVSTA set_io(PORTC, 0)
67+
#define clr_CONVSTA clear_io(PORTC, 0)
68+
#define tgl_CONVSTA toggle_io(PORTC, 0)
69+
#define read_CONVSTA read_io(PORTC, 0)
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7071
/* CONVSTB */
71-
#define set_CONVSTB set_io(PORTC, 1)
72+
#define set_CONVSTB set_io(PORTC, 1)
7273
#define clr_CONVSTB clear_io(PORTC, 1)
7374
#define tgl_CONVSTB toggle_io(PORTC, 1)
7475
#define read_CONVSTB read_io(PORTC, 1)
7576

76-
7777
/* MOSI */
7878
#define set_MOSI set_io(PORTC, 5)
7979
#define clr_MOSI clear_io(PORTC, 5)

‎Firmware/AnalogInput/interrupts.c

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@@ -54,7 +54,7 @@ ISR(PORTB_INT0_vect, ISR_NAKED)
5454
break;
5555

5656
case GM_DI0_RISE_CATCH_SAMPLE:
57-
set_CONVST;
57+
set_CONVSTA;
5858
set_CONVSTB;
5959
switch (app_regs.REG_TRIGGER_DESTINY)
6060
{
@@ -89,7 +89,7 @@ ISR(PORTB_INT0_vect, ISR_NAKED)
8989
break;
9090

9191
case GM_DI0_FALL_CATCH_SAMPLE:
92-
set_CONVST;
92+
set_CONVSTA;
9393
set_CONVSTB;
9494
switch (app_regs.REG_TRIGGER_DESTINY)
9595
{
@@ -115,7 +115,7 @@ ISR(PORTD_INT0_vect, ISR_NAKED)
115115
{
116116
if (!read_BUSY)
117117
{
118-
clr_CONVST;
118+
clr_CONVSTA;
119119
clr_CONVSTB;
120120

121121
switch (app_regs.REG_TRIGGER_DESTINY)

‎Firmware/AnalogInput/registers.xls

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