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td-shim: Migration build ResetVector.bin
Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Signed-off-by: Liu Jiang <gerry@linux.alibaba.com> Signed-off-by: haowei <WeiX.Hao@intel.com>
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‎td-shim/ResetVector/CommonMacros.inc

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;------------------------------------------------------------------------------
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; @file
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; Common macros used in the ResetVector VTF module.
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;
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; Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
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; SPDX-License-Identifier: BSD-2-Clause-Patent
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;
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;------------------------------------------------------------------------------
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%macro tdcall 0
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%if (USE_TDX_EMULATION != 0)
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vmcall
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%else
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db 0x66,0x0f,0x01,0xcc
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%endif
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%endmacro
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%define ADDR16_OF(x) (0x10000 - fourGigabytes + x)
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%define ADDR_OF(x) (0x100000000 - fourGigabytes + x)
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%macro OneTimeCall 1
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jmp %1
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%1 %+ OneTimerCallReturn:
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%endmacro
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%macro OneTimeCallRet 1
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jmp %1 %+ OneTimerCallReturn
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%endmacro
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CommandOffset equ 00h
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ApicidOffset equ 04h
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WakeupVectorOffset equ 08h
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OSArgsOffset equ 10h
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FirmwareArgsOffset equ 800h
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WakeupArgsRelocatedMailBox equ 800h
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ApWorkingStackStart equ 800h
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CpuArrivalOffset equ 900h
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CpusExitingOffset equ 0a00h
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TalliesOffset equ 0a08h
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MpProtectedModeWakeupCommandNoop equ 0
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MpProtectedModeWakeupCommandWakeup equ 1
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MpProtectedModeWakeupCommandSleep equ 2
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MpProtectedModeWakeupCommandAssignWork equ 3
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MpProtectedModeWakeupCommandCheck equ 4
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MailboxApicIdInvalid equ 0xffffffff
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MailboxApicidBroadcast equ 0xfffffffe
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%macro simple_spinlock 3
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mov edx, %1
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mov eax, 0
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mov ebx, 1
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%%testlock:
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lock cmpxchg [edx], ebx
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jnz %3
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mov eax, 0
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mov ebx, 1
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lock cmpxchg [edx+4], ebx
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jnz %2
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%%firstone:
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pause
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%endmacro
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%macro simple_releaselock 3
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%2:
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mov eax, 1
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mov edx, %1
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jmp %%testlock
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%3:
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pause
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mov eax, 0
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%%testlock:
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mov ebx, 0
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lock cmpxchg [edx], ebx
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jnz %3
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%endmacro
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%define PAGE_PRESENT 0x01
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%define PAGE_READ_WRITE 0x02
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%define PAGE_USER_SUPERVISOR 0x04
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%define PAGE_WRITE_THROUGH 0x08
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%define PAGE_CACHE_DISABLE 0x010
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%define PAGE_ACCESSED 0x020
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%define PAGE_DIRTY 0x040
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%define PAGE_PAT 0x080
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%define PAGE_GLOBAL 0x0100
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%define PAGE_2M_MBO 0x080
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%define PAGE_2M_PAT 0x01000
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%define PAGE_2M_PDE_ATTR (PAGE_2M_MBO + \
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PAGE_ACCESSED + \
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PAGE_DIRTY + \
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PAGE_READ_WRITE + \
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PAGE_PRESENT)
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%define PAGE_PDP_ATTR (PAGE_ACCESSED + \
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PAGE_READ_WRITE + \
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PAGE_PRESENT)
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%define PT_ADDR(Base,Offset) ((Base) + (Offset))
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%macro clear_pagetables 1
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mov ecx, 6 * 0x1000 / 4
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xor eax, eax
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%%clearloop:
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mov dword[ecx * 4 + PT_ADDR (%1,0) - 4], eax
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loop %%clearloop
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%endmacro
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%macro init_l4_l3_page_tables 2
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;
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; Top level Page Directory Pointers (1 * 512GB entry)
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;
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mov dword[PT_ADDR (%1,0)], PT_ADDR (%1,0x1000) + PAGE_PDP_ATTR
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mov dword[PT_ADDR (%1,4)], %2
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;
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; Next level Page Directory Pointers (4 * 1GB entries => 4GB)
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;
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mov dword[PT_ADDR (%1,0x1000)], PT_ADDR (%1,0x2000) + PAGE_PDP_ATTR
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mov dword[PT_ADDR (%1,0x1004)], %2
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mov dword[PT_ADDR (%1,0x1008)], PT_ADDR (%1,0x3000) + PAGE_PDP_ATTR
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mov dword[PT_ADDR (%1,0x100C)], %2
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mov dword[PT_ADDR (%1,0x1010)], PT_ADDR (%1,0x4000) + PAGE_PDP_ATTR
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mov dword[PT_ADDR (%1,0x1014)], %2
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mov dword[PT_ADDR (%1,0x1018)], PT_ADDR (%1,0x5000) + PAGE_PDP_ATTR
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mov dword[PT_ADDR (%1,0x101C)], %2
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%endmacro
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%macro init_l2_page_tables 2
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;
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; Page Table Entries (2048 * 2MB entries => 4GB)
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;
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mov ecx, 0x800
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%%loop:
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mov eax, ecx
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dec eax
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shl eax, 21
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add eax, PAGE_2M_PDE_ATTR
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mov [ecx * 8 + PT_ADDR (%1,0x2000 - 8)], eax
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mov dword[(ecx * 8 + PT_ADDR (%1,0x2000 - 8)) + 4], %2
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loop %%loop
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%endmacro
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%macro initialize_page_tables 2
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clear_pagetables %1
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init_l4_l3_page_tables %1,%2
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init_l2_page_tables %1,%2
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%endmacro
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%define EFI_HOB_TYPE_HANDOFF 0x0001
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%define EFI_HOB_TYPE_MEMORY_ALLOCATION 0x0002
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%define EFI_HOB_TYPE_RESOURCE_DESCRIPTOR 0x0003
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%define EFI_HOB_TYPE_GUID_EXTENSION 0x0004
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%define EFI_HOB_TYPE_FV 0x0005
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%define EFI_HOB_TYPE_CPU 0x0006
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%define EFI_HOB_TYPE_MEMORY_POOL 0x0007
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%define EFI_HOB_TYPE_FV2 0x0009
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%define EFI_HOB_TYPE_LOAD_PEIM_UNUSED 0x000A
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%define EFI_HOB_TYPE_UEFI_CAPSULE 0x000B
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%define EFI_HOB_TYPE_FV3 0x000C
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%define EFI_HOB_TYPE_UNUSED 0xFFFE
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%define EFI_HOB_TYPE_END_OF_HOB_LIST 0xFFFF
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%define EFI_RESOURCE_SYSTEM_MEMORY 0x00000000
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%define EFI_RESOURCE_MEMORY_MAPPED_IO 0x00000001
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%define EFI_RESOURCE_IO 0x00000002
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%define EFI_RESOURCE_FIRMWARE_DEVICE 0x00000003
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%define EFI_RESOURCE_MEMORY_MAPPED_IO_PORT 0x00000004
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%define EFI_RESOURCE_MEMORY_RESERVED 0x00000005
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%define EFI_RESOURCE_IO_RESERVED 0x00000006
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%define EFI_RESOURCE_MAX_MEMORY_TYPE 0x00000007
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%define EFI_RESOURCE_ATTRIBUTE_PRESENT 0x00000001
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%define EFI_RESOURCE_ATTRIBUTE_INITIALIZED 0x00000002
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%define EFI_RESOURCE_ATTRIBUTE_TESTED 0x00000004
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%define EFI_RESOURCE_ATTRIBUTE_READ_PROTECTED 0x00000080
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%define EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE 0x00000400
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%define EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE 0x00000800
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%define EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE 0x00001000
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%define EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE 0x00002000
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%define EFI_IO_ATTR (EFI_RESOURCE_ATTRIBUTE_PRESENT + \
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EFI_RESOURCE_ATTRIBUTE_INITIALIZED + \
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EFI_RESOURCE_ATTRIBUTE_TESTED + \
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EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE)
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%define EFI_LOW_MEM_ATTR (EFI_RESOURCE_ATTRIBUTE_PRESENT + \
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EFI_RESOURCE_ATTRIBUTE_INITIALIZED + \
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EFI_RESOURCE_ATTRIBUTE_TESTED + \
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EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE + \
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EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE + \
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EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE + \
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EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE)
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%define TDCALL_TDINFO 0x1
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%define TDCALL_TDACCEPTPAGE 0x6

‎td-shim/ResetVector/DebugDisabled.asm

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;------------------------------------------------------------------------------
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; @file
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; Debug disabled
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;
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; Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
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; SPDX-License-Identifier: BSD-2-Clause-Patent
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;
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;------------------------------------------------------------------------------
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BITS 16
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%macro debugInitialize 0
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;
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; No initialization is required
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;
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%endmacro
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%macro debugShowPostCode 1
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%endmacro

‎td-shim/ResetVector/Ia32/Flat32ToFlat64.asm

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;------------------------------------------------------------------------------
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; @file
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; Transition from 32 bit flat protected mode into 64 bit flat protected mode
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;
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; Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
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; SPDX-License-Identifier: BSD-2-Clause-Patent
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;
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;------------------------------------------------------------------------------
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BITS 32
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;
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; Modified: EAX. ECX
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;
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Transition32FlatTo64Flat:
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mov eax, cr4
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bts eax, 5 ; enable PAE
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;
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; esp [6:0] holds gpaw, if it is at least 52 bits, need to set
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; LA57 and use 5-level paging
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;
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mov ecx, esp
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and ecx, 0x2f
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cmp ecx, 52
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jl .set_cr4
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bts eax, 12
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.set_cr4:
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mov cr4, eax
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mov ecx, ADDR_OF(TopLevelPageDirectory)
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;
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; if we just set la57, we are ok, if using 4-level paging, adjust top-level page directory
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;
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bt eax, 12
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jc .set_cr3
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add ecx, 0x1000
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.set_cr3:
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mov cr3, ecx
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mov eax, cr0
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bts eax, 31 ; set PG
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mov cr0, eax ; enable paging
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jmp LINEAR_CODE64_SEL:ADDR_OF(jumpTo64BitAndLandHere)
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BITS 64
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jumpTo64BitAndLandHere:
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debugShowPostCode POSTCODE_64BIT_MODE
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OneTimeCallRet Transition32FlatTo64Flat

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