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| 1 | +/*************************************************************************** |
| 2 | + * Copyright (C) 2019 PCSX-Redux authors * |
| 3 | + * * |
| 4 | + * This program is free software; you can redistribute it and/or modify * |
| 5 | + * it under the terms of the GNU General Public License as published by * |
| 6 | + * the Free Software Foundation; either version 2 of the License, or * |
| 7 | + * (at your option) any later version. * |
| 8 | + * * |
| 9 | + * This program is distributed in the hope that it will be useful, * |
| 10 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of * |
| 11 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * |
| 12 | + * GNU General Public License for more details. * |
| 13 | + * * |
| 14 | + * You should have received a copy of the GNU General Public License * |
| 15 | + * along with this program; if not, write to the * |
| 16 | + * Free Software Foundation, Inc., * |
| 17 | + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * |
| 18 | + ***************************************************************************/ |
| 19 | + |
| 20 | +#include <fileio.h> |
| 21 | +#include <ps1hwregs.h> |
| 22 | +#include <ps1sdk.h> |
| 23 | +#include <serialio.h> |
| 24 | +#include <stdio.h> |
| 25 | + |
| 26 | +#include "common/hardware/cop0.h" |
| 27 | + |
| 28 | +typedef struct { |
| 29 | + uint32_t inited, mode, ctrl, baud; |
| 30 | +} port_config_t; |
| 31 | + |
| 32 | +static port_config_t config = {0, 0, 0, 0}; |
| 33 | + |
| 34 | +#define SIO1_BAUD_DIV (2073600) |
| 35 | + |
| 36 | +static inline void sio_set_ctrl_m(uint16_t mask, uint16_t ctrl) { |
| 37 | + *R_PS1_SIO1_CTRL = ((*R_PS1_SIO1_CTRL) & mask) | ctrl; |
| 38 | +} |
| 39 | + |
| 40 | +static inline void sio_set_ctrl(uint16_t ctrl) { *R_PS1_SIO1_CTRL = ctrl; } |
| 41 | +static inline void sio_set_mode(uint16_t mode) { *R_PS1_SIO1_MODE = (mode & (~3)) | SIO_MODE_BR_16; } |
| 42 | +static inline void sio_set_baud(uint32_t baud) { *R_PS1_SIO1_BAUD = SIO1_BAUD_DIV / baud; } |
| 43 | + |
| 44 | +static inline void sio_set_data(uint8_t d) { *R_PS1_SIO1_DATA = d; } |
| 45 | + |
| 46 | +/* |
| 47 | + * the sio_put_xxx functions not only write the value to the register but also update the config value for that register |
| 48 | + */ |
| 49 | +static inline void sio_put_baud(uint32_t baud) { |
| 50 | + config.baud = baud; |
| 51 | + sio_set_baud(config.baud); |
| 52 | +} |
| 53 | + |
| 54 | +static inline void sio_put_ctrl(uint16_t mask, uint16_t ctrl) { |
| 55 | + config.ctrl = ctrl; |
| 56 | + sio_set_ctrl_m(mask, config.ctrl); |
| 57 | +} |
| 58 | + |
| 59 | +static inline void sio_put_mode(uint16_t mode) { |
| 60 | + // bits 0 and 1 should always be 0 and 1, respectively |
| 61 | + // this apparently corresponds to "baud rate multiplier 16" |
| 62 | + config.mode = mode; |
| 63 | + sio_set_mode(config.mode); |
| 64 | +} |
| 65 | + |
| 66 | +static inline uint16_t sio_get_stat(void) { return *R_PS1_SIO1_STAT & SIO_STAT_MASK; } |
| 67 | + |
| 68 | +static inline uint8_t sio_get_data(void) { return *R_PS1_SIO1_DATA; } |
| 69 | + |
| 70 | +static inline uint16_t sio_get_ctrl(void) { |
| 71 | + uint16_t d = *R_PS1_SIO1_CTRL; |
| 72 | + return |
| 73 | + //(((d >> 5) & 1) << 1) | ((d >> 1) & 1); |
| 74 | + ((d & SIO_CTRL_RTR_EN) >> 4) | ((d & SIO_CTRL_DTR_EN) >> 1); |
| 75 | +} |
| 76 | + |
| 77 | +static inline uint16_t sio_get_mode(void) { return *R_PS1_SIO1_MODE & 0x1FFF; } |
| 78 | + |
| 79 | +static inline uint32_t sio_get_baud(void) { return SIO1_BAUD_DIV / (*R_PS1_SIO1_BAUD); } |
| 80 | + |
| 81 | +void sio_reset(void) { *R_PS1_SIO1_CTRL = SIO_CTRL_RESET_INT | SIO_CTRL_RESET_ERR; } |
| 82 | + |
| 83 | +// this needs more investigation. |
| 84 | +void sio_reset_driver(void) { |
| 85 | + sio_set_ctrl(SIO_CTRL_RESET_INT); |
| 86 | + sio_set_mode(0x0000); |
| 87 | + sio_set_baud(0x0000); |
| 88 | +} |
| 89 | + |
| 90 | +// I think this is wrong and should be the same as sio_reset(). |
| 91 | +void sio_clear_error(void) { sio_set_ctrl(SIO_CTRL_RESET_ERR); } |
| 92 | + |
| 93 | +// this should probably check STAT for errors. |
| 94 | +int sio_peek8(uint32_t timeout) { |
| 95 | + int ret = -1; |
| 96 | + |
| 97 | + // this may not be necessary. Some UARTs won't transfer if yout don't though. |
| 98 | + |
| 99 | + // RTR(Ready To Receive akia "RTS"/Request to Send): on |
| 100 | + sio_set_ctrl_m(~(SIO_CTRL_RTR_EN), SIO_CTRL_RTR_EN); |
| 101 | + |
| 102 | + // wait for data in the RX FIFO |
| 103 | + |
| 104 | + if (timeout == 0) { |
| 105 | + while (!(sio_get_stat() & SIO_STAT_RX_RDY)) |
| 106 | + ; |
| 107 | + } else { |
| 108 | + uint32_t tries = 0; |
| 109 | + while (!(sio_get_stat() & SIO_STAT_RX_RDY)) { |
| 110 | + if (++tries >= timeout) goto _done; |
| 111 | + } |
| 112 | + } |
| 113 | + |
| 114 | + // pop a byte from the RX FIFO |
| 115 | + ret = *R_PS1_SIO1_DATA; |
| 116 | + |
| 117 | +_done: |
| 118 | + // RTR/RTS: off |
| 119 | + sio_set_ctrl_m(~(SIO_CTRL_RTR_EN), 0); |
| 120 | + |
| 121 | + return ret; |
| 122 | +} |
| 123 | + |
| 124 | +int sio_poke8(uint8_t data, uint32_t timeout) { |
| 125 | + volatile uint8_t d; |
| 126 | + |
| 127 | + if (sio_get_stat() & (SIO_STAT_RX_OVRN_ERR | SIO_STAT_FRAME_ERR | SIO_STAT_PARITY_ERR)) { |
| 128 | + // RX Overrun, Frame Error or Parity Error occured |
| 129 | + |
| 130 | + // I guess this is to preserve the data that's currently in the TX FIFO? |
| 131 | + d = *R_PS1_SIO1_DATA; |
| 132 | + |
| 133 | + while (sio_get_stat() & (SIO_STAT_RX_OVRN_ERR | SIO_STAT_FRAME_ERR | SIO_STAT_PARITY_ERR)) { |
| 134 | + // reset the interrupt and error |
| 135 | + sio_reset(); |
| 136 | + |
| 137 | + delay_ms(5); |
| 138 | + |
| 139 | + // restore the TX FIFO? |
| 140 | + *R_PS1_SIO1_DATA = d; |
| 141 | + |
| 142 | + // restore mode and ctrl |
| 143 | + sio_set_mode(config.mode); |
| 144 | + sio_set_ctrl(config.ctrl); |
| 145 | + } |
| 146 | + } |
| 147 | + |
| 148 | + // FIXME: what happens if the CTRL SIO_CTRL_TX_EN isn't set?? |
| 149 | + |
| 150 | + if (timeout == 0) { |
| 151 | + while (!(sio_get_stat() & SIO_STAT_TX_RDY)) |
| 152 | + ; |
| 153 | + } else { |
| 154 | + uint32_t tries = 0; |
| 155 | + while (!(sio_get_stat() & SIO_STAT_TX_RDY)) { |
| 156 | + if (++tries >= timeout) return -2; |
| 157 | + } |
| 158 | + } |
| 159 | + |
| 160 | + // push the byte into the TX FIFO |
| 161 | + *R_PS1_SIO1_DATA = data; |
| 162 | + return data; |
| 163 | +} |
| 164 | + |
| 165 | +uint8_t sio_get_byte(void) { |
| 166 | + uint8_t ret; |
| 167 | + |
| 168 | + // RTR(Ready To Receive akia "RTS"/Request to Send): on |
| 169 | + sio_set_ctrl_m(~(SIO_CTRL_RTR_EN), SIO_CTRL_RTR_EN); |
| 170 | + |
| 171 | + // wait for data in the RX FIFO |
| 172 | + |
| 173 | + while (!(sio_get_stat() & SIO_STAT_RX_RDY)) |
| 174 | + ; |
| 175 | + |
| 176 | + // pop a byte from the RX FIFO |
| 177 | + ret = *R_PS1_SIO1_DATA; |
| 178 | + |
| 179 | + // RTR/RTS: off |
| 180 | + sio_set_ctrl_m(~(SIO_CTRL_RTR_EN), 0); |
| 181 | + |
| 182 | + return ret; |
| 183 | +} |
| 184 | + |
| 185 | +void sio_put_byte(uint8_t d) { |
| 186 | + while ((sio_get_stat() & (SIO_STAT_TX_EMPTY | SIO_STAT_TX_RDY)) != (SIO_STAT_TX_EMPTY | SIO_STAT_TX_RDY)) |
| 187 | + ; |
| 188 | + *R_PS1_SIO1_DATA = d; |
| 189 | +} |
| 190 | + |
| 191 | +void init_sio(uint32_t baud) |
| 192 | +{ |
| 193 | + /* initialize SIO1 with RX and TX FIFOs enabled */ |
| 194 | + *R_PS1_SIO1_CTRL = (SIO_CTRL_RX_EN | SIO_CTRL_TX_EN); |
| 195 | + /* 8bit, no-parity, 1 stop-bit */ |
| 196 | + *R_PS1_SIO1_MODE = (SIO_MODE_CHLEN_8 | SIO_MODE_P_NONE | SIO_MODE_SB_1 | SIO_MODE_BR_16); |
| 197 | + *R_PS1_SIO1_BAUD = (2073600/baud); |
| 198 | +} |
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