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nicolasnoblenicolasnoble
committed
Dynarec LWR/LWL rework.
1 parent 9639d12 commit 771f35b

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3 files changed

+112
-111
lines changed

3 files changed

+112
-111
lines changed

‎src/core/ix86/iR3000A.cc

Lines changed: 97 additions & 99 deletions
Original file line numberDiff line numberDiff line change
@@ -202,10 +202,7 @@ class X86DynaRecCPU : public PCSX::R3000Acpu {
202202
void recLHU();
203203
void recLW();
204204

205-
void iLWLk(uint32_t shift);
206205
void recLWL();
207-
208-
void iLWRk(uint32_t shift);
209206
void recLWR();
210207

211208
void recSB();
@@ -1737,17 +1734,6 @@ void X86DynaRecCPU::recLW() {
17371734
gen.ADD32ItoR(PCSX::ix86::ESP, 4);
17381735
}
17391736

1740-
void X86DynaRecCPU::iLWLk(uint32_t shift) {
1741-
if (IsConst(_Rt_)) {
1742-
gen.MOV32ItoR(PCSX::ix86::ECX, m_iRegs[_Rt_].k);
1743-
} else {
1744-
gen.MOV32MtoR(PCSX::ix86::ECX, (uint32_t)&m_psxRegs.GPR.r[_Rt_]);
1745-
}
1746-
gen.AND32ItoR(PCSX::ix86::ECX, g_LWL_MASK[shift]);
1747-
gen.SHL32ItoR(PCSX::ix86::EAX, g_LWL_SHIFT[shift]);
1748-
gen.OR32RtoR(PCSX::ix86::EAX, PCSX::ix86::ECX);
1749-
}
1750-
17511737
void X86DynaRecCPU::recLWL() {
17521738
// Rt = Rt Merge mem[Rs + Im]
17531739

@@ -1760,24 +1746,27 @@ void X86DynaRecCPU::recLWL() {
17601746
if (IsConst(_Rs_)) {
17611747
uint32_t addr = m_iRegs[_Rs_].k + _Imm_;
17621748
int t = addr >> 16;
1749+
auto iLWLk = [&](uint32_t shift, uint32_t ptr) {
1750+
gen.MOV32MtoR(PCSX::ix86::EAX, ptr);
1751+
if (LWL_SHIFT[shift]) gen.SHL32ItoR(PCSX::ix86::EAX, LWL_SHIFT[shift]);
1752+
gen.MOV32RtoR(PCSX::ix86::EDI, PCSX::ix86::EAX);
1753+
if (LWL_MASK_INDEX[shift]) {
1754+
gen.MOV32ItoR(PCSX::ix86::ECX, LWL_MASK_INDEX[shift]);
1755+
gen.SHL32ItoR(PCSX::ix86::ECX, 16);
1756+
gen.OR32RtoR(PCSX::ix86::EBX, PCSX::ix86::ECX);
1757+
}
1758+
};
17631759

17641760
if ((t & 0x1fe0) == 0) {
1765-
gen.MOV32MtoR(PCSX::ix86::EAX, (uint32_t)&PCSX::g_emulator.m_psxMem->g_psxM[addr & 0x1ffffc]);
1766-
iLWLk(addr & 3);
1767-
gen.MOV32RtoR(PCSX::ix86::EDI, PCSX::ix86::EAX);
1761+
iLWLk(addr & 3, (uint32_t)&PCSX::g_emulator.m_psxMem->g_psxM[addr & 0x1ffffc]);
17681762
return;
17691763
}
17701764
if (t == 0x1f80 && addr < 0x1f801000) {
1771-
gen.MOV32MtoR(PCSX::ix86::EAX, (uint32_t)&PCSX::g_emulator.m_psxMem->g_psxH[addr & 0xffc]);
1772-
iLWLk(addr & 3);
1773-
gen.MOV32RtoM(PCSX::ix86::EDI, PCSX::ix86::EAX);
1765+
iLWLk(addr & 3, (uint32_t)&PCSX::g_emulator.m_psxMem->g_psxH[addr & 0xffc]);
17741766
return;
17751767
}
1776-
}
1777-
1778-
if (IsConst(_Rs_))
17791768
gen.MOV32ItoR(PCSX::ix86::EAX, m_iRegs[_Rs_].k + _Imm_);
1780-
else {
1769+
} else {
17811770
gen.MOV32MtoR(PCSX::ix86::EAX, (uint32_t)&m_psxRegs.GPR.r[_Rs_]);
17821771
if (_Imm_) gen.ADD32ItoR(PCSX::ix86::EAX, _Imm_);
17831772
}
@@ -1791,36 +1780,21 @@ void X86DynaRecCPU::recLWL() {
17911780
gen.POP32R(PCSX::ix86::EDX);
17921781
gen.AND32ItoR(PCSX::ix86::EDX, 0x3); // shift = addr & 3;
17931782

1794-
gen.MOV32ItoR(PCSX::ix86::ECX, (uint32_t)g_LWL_SHIFT);
1783+
gen.MOV32ItoR(PCSX::ix86::ECX, (uint32_t)LWL_SHIFT);
17951784
gen.MOV32RmStoR(PCSX::ix86::ECX, PCSX::ix86::ECX, PCSX::ix86::EDX, 2);
1796-
gen.SHL32CLtoR(PCSX::ix86::EAX); // mem(PCSX::ix86::EAX) << g_LWL_SHIFT[shift]
1785+
gen.SHL32CLtoR(PCSX::ix86::EAX); // mem(PCSX::ix86::EAX) << LWL_SHIFT[shift]
1786+
gen.MOV32RtoR(PCSX::ix86::EDI, PCSX::ix86::EAX);
17971787

1798-
gen.MOV32ItoR(PCSX::ix86::ECX, (uint32_t)g_LWL_MASK);
1788+
gen.MOV32ItoR(PCSX::ix86::ECX, (uint32_t)LWL_MASK_INDEX);
17991789
gen.MOV32RmStoR(PCSX::ix86::ECX, PCSX::ix86::ECX, PCSX::ix86::EDX, 2);
1800-
if (IsConst(_Rt_)) {
1801-
gen.MOV32ItoR(PCSX::ix86::EDX, m_iRegs[_Rt_].k);
1802-
} else {
1803-
gen.MOV32MtoR(PCSX::ix86::EDX, (uint32_t)&m_psxRegs.GPR.r[_Rt_]);
1804-
}
1805-
gen.AND32RtoR(PCSX::ix86::EDX, PCSX::ix86::ECX); // _rRt_ & g_LWL_MASK[shift]
1806-
gen.OR32RtoR(PCSX::ix86::EAX, PCSX::ix86::EDX);
1807-
gen.MOV32RtoR(PCSX::ix86::EDI, PCSX::ix86::EAX);
1790+
gen.SHL32ItoR(PCSX::ix86::ECX, 16);
1791+
gen.AND32ItoR(PCSX::ix86::EBX, 0xffff);
1792+
gen.OR32RtoR(PCSX::ix86::EBX, PCSX::ix86::ECX);
18081793
} else {
18091794
gen.ADD32ItoR(PCSX::ix86::ESP, 8);
18101795
}
18111796
}
18121797

1813-
void X86DynaRecCPU::iLWRk(uint32_t shift) {
1814-
if (IsConst(_Rt_)) {
1815-
gen.MOV32ItoR(PCSX::ix86::ECX, m_iRegs[_Rt_].k);
1816-
} else {
1817-
gen.MOV32MtoR(PCSX::ix86::ECX, (uint32_t)&m_psxRegs.GPR.r[_Rt_]);
1818-
}
1819-
gen.AND32ItoR(PCSX::ix86::ECX, g_LWR_MASK[shift]);
1820-
gen.SHR32ItoR(PCSX::ix86::EAX, g_LWR_SHIFT[shift]);
1821-
gen.OR32RtoR(PCSX::ix86::EAX, PCSX::ix86::ECX);
1822-
}
1823-
18241798
void X86DynaRecCPU::recLWR() {
18251799
// Rt = Rt Merge mem[Rs + Im]
18261800

@@ -1834,23 +1808,27 @@ void X86DynaRecCPU::recLWR() {
18341808
uint32_t addr = m_iRegs[_Rs_].k + _Imm_;
18351809
int t = addr >> 16;
18361810

1837-
if ((t & 0x1fe0) == 0) {
1838-
gen.MOV32MtoR(PCSX::ix86::EAX, (uint32_t)&PCSX::g_emulator.m_psxMem->g_psxM[addr & 0x1ffffc]);
1839-
iLWRk(addr & 3);
1811+
auto iLWRk = [&](uint32_t shift, uint32_t ptr) {
1812+
gen.MOV32MtoR(PCSX::ix86::EAX, ptr);
1813+
if (LWR_SHIFT[shift]) gen.SHL32ItoR(PCSX::ix86::EAX, LWR_SHIFT[shift]);
18401814
gen.MOV32RtoR(PCSX::ix86::EDI, PCSX::ix86::EAX);
1815+
if (LWR_MASK_INDEX[shift]) {
1816+
gen.MOV32ItoR(PCSX::ix86::ECX, LWR_MASK_INDEX[shift]);
1817+
gen.SHR32ItoR(PCSX::ix86::ECX, 16);
1818+
gen.OR32RtoR(PCSX::ix86::EBX, PCSX::ix86::ECX);
1819+
}
1820+
};
1821+
1822+
if ((t & 0x1fe0) == 0) {
1823+
iLWRk(addr & 3, (uint32_t)&PCSX::g_emulator.m_psxMem->g_psxM[addr & 0x1ffffc]);
18411824
return;
18421825
}
18431826
if (t == 0x1f80 && addr < 0x1f801000) {
1844-
gen.MOV32MtoR(PCSX::ix86::EAX, (uint32_t)&PCSX::g_emulator.m_psxMem->g_psxH[addr & 0xffc]);
1845-
iLWRk(addr & 3);
1846-
gen.MOV32RtoR(PCSX::ix86::EDI, PCSX::ix86::EAX);
1827+
iLWRk(addr & 3, (uint32_t)&PCSX::g_emulator.m_psxMem->g_psxH[addr & 0xffc]);
18471828
return;
18481829
}
1849-
}
1850-
1851-
if (IsConst(_Rs_))
18521830
gen.MOV32ItoR(PCSX::ix86::EAX, m_iRegs[_Rs_].k + _Imm_);
1853-
else {
1831+
} else {
18541832
gen.MOV32MtoR(PCSX::ix86::EAX, (uint32_t)&m_psxRegs.GPR.r[_Rs_]);
18551833
if (_Imm_) gen.ADD32ItoR(PCSX::ix86::EAX, _Imm_);
18561834
}
@@ -1864,21 +1842,16 @@ void X86DynaRecCPU::recLWR() {
18641842
gen.POP32R(PCSX::ix86::EDX);
18651843
gen.AND32ItoR(PCSX::ix86::EDX, 0x3); // shift = addr & 3;
18661844

1867-
gen.MOV32ItoR(PCSX::ix86::ECX, (uint32_t)g_LWR_SHIFT);
1845+
gen.MOV32ItoR(PCSX::ix86::ECX, (uint32_t)LWR_SHIFT);
18681846
gen.MOV32RmStoR(PCSX::ix86::ECX, PCSX::ix86::ECX, PCSX::ix86::EDX, 2);
1869-
gen.SHR32CLtoR(PCSX::ix86::EAX); // mem(PCSX::ix86::EAX) >> g_LWR_SHIFT[shift]
1847+
gen.SHR32CLtoR(PCSX::ix86::EAX); // mem(PCSX::ix86::EAX) << LWR_SHIFT[shift]
1848+
gen.MOV32RtoR(PCSX::ix86::EDI, PCSX::ix86::EAX);
18701849

1871-
gen.MOV32ItoR(PCSX::ix86::ECX, (uint32_t)g_LWR_MASK);
1850+
gen.MOV32ItoR(PCSX::ix86::ECX, (uint32_t)LWR_MASK_INDEX);
18721851
gen.MOV32RmStoR(PCSX::ix86::ECX, PCSX::ix86::ECX, PCSX::ix86::EDX, 2);
1873-
1874-
if (IsConst(_Rt_)) {
1875-
gen.MOV32ItoR(PCSX::ix86::EDX, m_iRegs[_Rt_].k);
1876-
} else {
1877-
gen.MOV32MtoR(PCSX::ix86::EDX, (uint32_t)&m_psxRegs.GPR.r[_Rt_]);
1878-
}
1879-
gen.AND32RtoR(PCSX::ix86::EDX, PCSX::ix86::ECX); // _rRt_ & g_LWR_MASK[shift]
1880-
gen.OR32RtoR(PCSX::ix86::EAX, PCSX::ix86::EDX);
1881-
gen.MOV32RtoR(PCSX::ix86::EDI, PCSX::ix86::EAX);
1852+
gen.SHL32ItoR(PCSX::ix86::ECX, 16);
1853+
gen.AND32ItoR(PCSX::ix86::EBX, 0xffff);
1854+
gen.OR32RtoR(PCSX::ix86::EBX, PCSX::ix86::ECX);
18821855
} else {
18831856
gen.ADD32ItoR(PCSX::ix86::ESP, 8);
18841857
}
@@ -2085,8 +2058,8 @@ void X86DynaRecCPU::iSWLk(uint32_t shift) {
20852058
} else {
20862059
gen.MOV32MtoR(PCSX::ix86::ECX, (uint32_t)&m_psxRegs.GPR.r[_Rt_]);
20872060
}
2088-
gen.SHR32ItoR(PCSX::ix86::ECX, g_SWL_SHIFT[shift]);
2089-
gen.AND32ItoR(PCSX::ix86::EAX, g_SWL_MASK[shift]);
2061+
gen.SHR32ItoR(PCSX::ix86::ECX, SWL_SHIFT[shift]);
2062+
gen.AND32ItoR(PCSX::ix86::EAX, SWL_MASK[shift]);
20902063
gen.OR32RtoR(PCSX::ix86::EAX, PCSX::ix86::ECX);
20912064
}
20922065

@@ -2129,18 +2102,18 @@ void X86DynaRecCPU::recSWL() {
21292102
gen.POP32R(PCSX::ix86::EDX);
21302103
gen.AND32ItoR(PCSX::ix86::EDX, 0x3); // shift = addr & 3;
21312104

2132-
gen.MOV32ItoR(PCSX::ix86::ECX, (uint32_t)g_SWL_MASK);
2105+
gen.MOV32ItoR(PCSX::ix86::ECX, (uint32_t)SWL_MASK);
21332106
gen.MOV32RmStoR(PCSX::ix86::ECX, PCSX::ix86::ECX, PCSX::ix86::EDX, 2);
2134-
gen.AND32RtoR(PCSX::ix86::EAX, PCSX::ix86::ECX); // mem & g_SWL_MASK[shift]
2107+
gen.AND32RtoR(PCSX::ix86::EAX, PCSX::ix86::ECX); // mem & SWL_MASK[shift]
21352108

2136-
gen.MOV32ItoR(PCSX::ix86::ECX, (uint32_t)g_SWL_SHIFT);
2109+
gen.MOV32ItoR(PCSX::ix86::ECX, (uint32_t)SWL_SHIFT);
21372110
gen.MOV32RmStoR(PCSX::ix86::ECX, PCSX::ix86::ECX, PCSX::ix86::EDX, 2);
21382111
if (IsConst(_Rt_)) {
21392112
gen.MOV32ItoR(PCSX::ix86::EDX, m_iRegs[_Rt_].k);
21402113
} else {
21412114
gen.MOV32MtoR(PCSX::ix86::EDX, (uint32_t)&m_psxRegs.GPR.r[_Rt_]);
21422115
}
2143-
gen.SHR32CLtoR(PCSX::ix86::EDX); // _rRt_ >> g_SWL_SHIFT[shift]
2116+
gen.SHR32CLtoR(PCSX::ix86::EDX); // _rRt_ >> SWL_SHIFT[shift]
21442117

21452118
gen.OR32RtoR(PCSX::ix86::EAX, PCSX::ix86::EDX);
21462119
gen.PUSH32R(PCSX::ix86::EAX);
@@ -2164,8 +2137,8 @@ void X86DynaRecCPU::iSWRk(uint32_t shift) {
21642137
} else {
21652138
gen.MOV32MtoR(PCSX::ix86::ECX, (uint32_t)&m_psxRegs.GPR.r[_Rt_]);
21662139
}
2167-
gen.SHL32ItoR(PCSX::ix86::ECX, g_SWR_SHIFT[shift]);
2168-
gen.AND32ItoR(PCSX::ix86::EAX, g_SWR_MASK[shift]);
2140+
gen.SHL32ItoR(PCSX::ix86::ECX, SWR_SHIFT[shift]);
2141+
gen.AND32ItoR(PCSX::ix86::EAX, SWR_MASK[shift]);
21692142
gen.OR32RtoR(PCSX::ix86::EAX, PCSX::ix86::ECX);
21702143
}
21712144

@@ -2208,18 +2181,18 @@ void X86DynaRecCPU::recSWR() {
22082181
gen.POP32R(PCSX::ix86::EDX);
22092182
gen.AND32ItoR(PCSX::ix86::EDX, 0x3); // shift = addr & 3;
22102183

2211-
gen.MOV32ItoR(PCSX::ix86::ECX, (uint32_t)g_SWR_MASK);
2184+
gen.MOV32ItoR(PCSX::ix86::ECX, (uint32_t)SWR_MASK);
22122185
gen.MOV32RmStoR(PCSX::ix86::ECX, PCSX::ix86::ECX, PCSX::ix86::EDX, 2);
2213-
gen.AND32RtoR(PCSX::ix86::EAX, PCSX::ix86::ECX); // mem & g_SWR_MASK[shift]
2186+
gen.AND32RtoR(PCSX::ix86::EAX, PCSX::ix86::ECX); // mem & SWR_MASK[shift]
22142187

2215-
gen.MOV32ItoR(PCSX::ix86::ECX, (uint32_t)g_SWR_SHIFT);
2188+
gen.MOV32ItoR(PCSX::ix86::ECX, (uint32_t)SWR_SHIFT);
22162189
gen.MOV32RmStoR(PCSX::ix86::ECX, PCSX::ix86::ECX, PCSX::ix86::EDX, 2);
22172190
if (IsConst(_Rt_)) {
22182191
gen.MOV32ItoR(PCSX::ix86::EDX, m_iRegs[_Rt_].k);
22192192
} else {
22202193
gen.MOV32MtoR(PCSX::ix86::EDX, (uint32_t)&m_psxRegs.GPR.r[_Rt_]);
22212194
}
2222-
gen.SHL32CLtoR(PCSX::ix86::EDX); // _rRt_ << g_SWR_SHIFT[shift]
2195+
gen.SHL32CLtoR(PCSX::ix86::EDX); // _rRt_ << SWR_SHIFT[shift]
22232196

22242197
gen.OR32RtoR(PCSX::ix86::EAX, PCSX::ix86::EDX);
22252198
gen.PUSH32R(PCSX::ix86::EAX);
@@ -3062,13 +3035,47 @@ void X86DynaRecCPU::recRecompile() {
30623035
unsigned count = 0;
30633036
gen.PUSH32R(PCSX::ix86::EBP);
30643037
gen.PUSH32R(PCSX::ix86::EBX);
3038+
gen.XOR32RtoR(PCSX::ix86::EBX, PCSX::ix86::EBX);
30653039
gen.PUSH32R(PCSX::ix86::ESI);
30663040
gen.PUSH32R(PCSX::ix86::EDI);
30673041
int8_t *endStackFramePtr = gen.x86GetPtr();
30683042

3069-
while (
3070-
((count < DYNAREC_BLOCK || m_delayedLoadInfo[0].active || m_delayedLoadInfo[1].active) && !m_stopRecompile) ||
3071-
m_nextIsDelaySlot) {
3043+
auto shouldContinue = [&]() {
3044+
if (m_nextIsDelaySlot) {
3045+
return true;
3046+
}
3047+
if (m_stopRecompile) {
3048+
return false;
3049+
}
3050+
if (count >= DYNAREC_BLOCK && !m_delayedLoadInfo[0].active && !m_delayedLoadInfo[1].active) {
3051+
return false;
3052+
}
3053+
return true;
3054+
};
3055+
3056+
auto processDelayedLoad = [&]() {
3057+
m_currentDelayedLoad ^= 1;
3058+
auto &delayedLoad = m_delayedLoadInfo[m_currentDelayedLoad];
3059+
if (delayedLoad.active) {
3060+
delayedLoad.active = false;
3061+
const unsigned index = delayedLoad.index;
3062+
gen.MOV32RtoR(PCSX::ix86::EDX, PCSX::ix86::EBX);
3063+
gen.AND32ItoR(PCSX::ix86::EDX, 0xffff);
3064+
gen.MOV32ItoR(PCSX::ix86::ECX, (uint32_t)MASKS);
3065+
gen.MOV32RmStoR(PCSX::ix86::EAX, PCSX::ix86::ECX, PCSX::ix86::EDX, 2);
3066+
if (IsConst(index)) {
3067+
gen.AND32ItoR(PCSX::ix86::EAX, m_iRegs[index].k);
3068+
gen.OR32RtoR(PCSX::ix86::EAX, PCSX::ix86::ESI);
3069+
gen.MOV32RtoM((uint32_t)&m_psxRegs.GPR.r[index], PCSX::ix86::EAX);
3070+
m_iRegs[index].state = ST_UNK;
3071+
} else {
3072+
gen.AND32RtoM((uint32_t)&m_psxRegs.GPR.r[index], PCSX::ix86::EAX);
3073+
gen.OR32RtoM((uint32_t)&m_psxRegs.GPR.r[index], PCSX::ix86::ESI);
3074+
}
3075+
}
3076+
};
3077+
3078+
while (shouldContinue()) {
30723079
if (m_nextIsDelaySlot) {
30733080
m_inDelaySlot = true;
30743081
m_nextIsDelaySlot = false;
@@ -3085,28 +3092,18 @@ void X86DynaRecCPU::recRecompile() {
30853092
(*this.*func)();
30863093

30873094
const bool isOtherActive = m_delayedLoadInfo[m_currentDelayedLoad].active;
3088-
m_currentDelayedLoad ^= 1;
3089-
auto &delayedLoad = m_delayedLoadInfo[m_currentDelayedLoad];
3090-
if (delayedLoad.active) {
3091-
delayedLoad.active = false;
3092-
const unsigned index = delayedLoad.index;
3093-
gen.MOV32RtoM((uint32_t)&m_psxRegs.GPR.r[index], PCSX::ix86::ESI);
3094-
m_iRegs[index].state = ST_UNK;
3095+
processDelayedLoad();
3096+
if (isOtherActive) {
3097+
gen.MOV32RtoR(PCSX::ix86::ESI, PCSX::ix86::EDI);
3098+
gen.SHR32ItoR(PCSX::ix86::EBX, 16);
30953099
}
3096-
if (isOtherActive) gen.MOV32RtoR(PCSX::ix86::ESI, PCSX::ix86::EDI);
30973100
}
30983101

30993102
// This is slightly inexact: if there's a delayed load in the delay slot of a branch,
31003103
// then we're flushing it early, before the next instruction had a chance to execute.
31013104
// This might be fine still, but it can be arranged if needed.
3102-
m_currentDelayedLoad ^= 1;
3103-
auto &delayedLoad = m_delayedLoadInfo[m_currentDelayedLoad];
3104-
if (delayedLoad.active) {
3105-
delayedLoad.active = false;
3106-
const unsigned index = delayedLoad.index;
3107-
gen.MOV32RtoM((uint32_t)&m_psxRegs.GPR.r[index], PCSX::ix86::ESI);
3108-
m_iRegs[index].state = ST_UNK;
3109-
}
3105+
processDelayedLoad();
3106+
31103107
iFlushRegs();
31113108

31123109
count = ((m_pc - old_pc) / 4) * PCSX::Emulator::BIAS;
@@ -3126,6 +3123,7 @@ void X86DynaRecCPU::recRecompile() {
31263123
gen.RET();
31273124
} else {
31283125
ptrdiff_t count = endStackFramePtr - startPtr;
3126+
(*(uint32_t *)PC_REC(old_pc)) = (uint32_t)endStackFramePtr;
31293127
gen.NOP(count, startPtr);
31303128
gen.RET();
31313129
}

‎src/core/psxinterpreter.cc

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -638,7 +638,7 @@ void InterpretedCPU::psxLWL() {
638638

639639
// load delay = 1 latency
640640
if (!_Rt_) return;
641-
_u32(delayedLoadRef(_Rt_, g_LWL_MASK[shift])) = mem << g_LWL_SHIFT[shift];
641+
_u32(delayedLoadRef(_Rt_, LWL_MASK[shift])) = mem << LWL_SHIFT[shift];
642642

643643
/*
644644
Mem = 1234. Reg = abcd
@@ -657,7 +657,7 @@ void InterpretedCPU::psxLWR() {
657657

658658
// load delay = 1 latency
659659
if (!_Rt_) return;
660-
_u32(delayedLoadRef(_Rt_, g_LWR_MASK[shift])) = mem >> g_LWR_SHIFT[shift];
660+
_u32(delayedLoadRef(_Rt_, LWR_MASK[shift])) = mem >> LWR_SHIFT[shift];
661661

662662
/*
663663
Mem = 1234. Reg = abcd
@@ -679,7 +679,7 @@ void InterpretedCPU::psxSWL() {
679679
uint32_t mem = PCSX::g_emulator.m_psxMem->psxMemRead32(addr & ~3);
680680

681681
PCSX::g_emulator.m_psxMem->psxMemWrite32(addr & ~3,
682-
(_u32(_rRt_) >> g_SWL_SHIFT[shift]) | (mem & g_SWL_MASK[shift]));
682+
(_u32(_rRt_) >> SWL_SHIFT[shift]) | (mem & SWL_MASK[shift]));
683683
/*
684684
Mem = 1234. Reg = abcd
685685
@@ -696,7 +696,7 @@ void InterpretedCPU::psxSWR() {
696696
uint32_t mem = PCSX::g_emulator.m_psxMem->psxMemRead32(addr & ~3);
697697

698698
PCSX::g_emulator.m_psxMem->psxMemWrite32(addr & ~3,
699-
(_u32(_rRt_) << g_SWR_SHIFT[shift]) | (mem & g_SWR_MASK[shift]));
699+
(_u32(_rRt_) << SWR_SHIFT[shift]) | (mem & SWR_MASK[shift]));
700700

701701
/*
702702
Mem = 1234. Reg = abcd

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